Dr. Mayank Shrivastava
Assistant Professor

Department of Electronic Systems Engineering
Indian Institute of Science Bangalore, 560012

 

Dr. Mayank Shrivastava
Assistant Professor
Department of Electronic Systems Engineering
Indian Institute of Science Bangalore, 560012
E-mail: mayank@dese.iisc.ernet.in
Contact: +91-80-2293-2732

Bio & Key Contributions

Dr. Mayank Shrivastava received his PhD degree from Indian Institute of Technology Bombay. He is among the first recipient of Indian section of American TR35 award (2010). He is also the first Indian to receive IEEE EDS Early Career Award (2015). In addition to this he is an IEEE Senior Member and has received several other awards and honors including 2008 best research paper award from Intel Corporation Asia academic forum; excellence in research award for his PhD thesis in 2010 and industrial impact award from IIT Bombay in 2008. Dr. Shrivastava’s current research deals with experimentation, design and modeling of beyond CMOS devices using Graphene and TMDCs, wide bandgap material based power semiconductor devices and ESD reliability in advanced and beyond CMOS nodes. He had held visiting positions in Infineon Technologies, Munich, Germany from April 2008 to October 2008 and again in May 2010 to July 2010. He worked for Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; and Intel Corp., Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined Indian Institute of Science as an assistant professor in year 2013 where he has established Advanced Nanoelectronic Device Research Group.

Dr. Shrivastava has over 65+ international publications and 35 patents. His one of the key contributions has been enablement and integration of nanoscale CMOS and power MOSFET devices in advanced CMOS nodes for System on Chip (SoC) applications. At Intel he was instrumental in developing and enabling integrated LDMOS devices for power management and RF modules, which in advance SoCs covers 20 – 30% of the chip area. In general his innovations on integrated high power switching and RF devices has enabled the semiconductor industries in the system on chip integration [T-ED Feb. 2010, Part I & II] [United States Patents # 8643090, 8097930] [T-ED 2015, Part I & II]. For example, in the past, various CMOS devices were proposed for integrated high power RF and switching applications. However, they used to fail under high current conditions, which seriously hampered the usefulness of these devices for advanced SoC products. Work done by Dr. Shrivastava provided a clear physical insight into the failure mechanism of Si power MOSFETs under extreme conditions [IEDM 2009] [IRPS 2009] [T-ED Sep. 2010 Part I & II] [IRPS 2010]. Going further, he used his theory and device insights to invent new class of robust & high performance power MOSFETs [United States Patents # 8536648 & 8354710] [IEDM 2014], which can be found in advanced SoC today. His research also changed the perception that robustness and performance cannot be achieved together, particularly for the high power-high frequency applications [T-ED Dec 2010]. Going one step further, he invented and designed first high power devices for FinFET technology [IEDM 2009] [EDL 2013] [United States Patents # 8664720 & 8455947]. As of now, Dr. Shrivastava holds over a dozen key LDMOS patents and most of the FinFET power MOSFET patents.These designs are used in current day system on chips.

At IISc Bangalore, these contributions of Dr. Shrivastava has lead to indigenous power SoC technology development initiative jointly with few strategic groups, which has resulted in a project funded by IMPRINT (worth 3 Crores). Dr. Shrivastava has further extended this work to other power semiconducting materials like Gallium Nitride, which has resulted in several international publications and patents. This is an outcome of a DST funded project (worth 10.2 Crores) lead by him at IISc Bangalore.

At the nanoelectronics front, Dr. Shrivastava has made major contributions towards next generation system on chips which involves novel device architectures, new materials and complex technology integration. In over 20 international publications including IEEE T-ED and IEDM, his work has highlighted the device-circuit co-design approach involving FinFETs and tunnel FETs for mixed signal SoC applications. The FinFET design concepts proposed by him have been found useful for mobile phone applications. These concepts have helped improving the battery standby time while improving the performance. Moreover, these works have established a methodology for understanding the impact of the process & device design on the circuit performance and provided insights into the effect of device level design optimization & reliability on the SoC performance. At IISc Dr. Shrivastava has extended these nanoelectronics activities to beyond Si materials as well, like Graphene, TMDCs and Phosphorene. RF FET technology developed at IISc Bangalore using CVD Graphene as channel material has broken past records including the best transistor performance reported by IBM T. J. Watson (USA) Center [IEDM 2016]. Dr. Shrivastava’s group has also developed a unique method to dope MoS2 for making contacts, which has lead to significant improvement in transistor performance. These are outcomes of another funded project (worth 4.7 Crores), which is led by Dr. Shrivastava at IISc Bangalore.

 

Work Experience

  • Assistant Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (September 2013 – Present).
  • Staff Engineer: Intel Corp. (MCG), Munich, Germany (April. 2013 – August 2013).
  • Senior Engineer: Intel Corp. (MCG), Munich, Germany (Sep. 2011 – March 2013).

Responsible for:

  • 28nm ESD protection concepts and library development.
  • 14nm ESD device and technology co-development, ESD device characterization, simulation and modeling topics.
  • Senior Engineer: Infineon Technologies, USA (Sep 2010 to Jan 2011) and Intel Corp. (MCG), USA, (Feb 2011 to Sep 2011).

Responsible for:

  • 28nm & 20nm ESD device and technology co-development, ESD device characterization, simulation and modeling topics at the IBM facilities in Essex Junction, VT and Hopewell Junction, NY, USA under the International Semiconductor Development Alliance.
  • Visiting Scholar: Infineon Technologies, Munich, Germany. April 2008 to Oct 2008 and again from May 2010 to July 2010.
Research Interest

Thrust Areas

  • Graphene, Carbon Nanotubes and novel 1D/2D materials
  • Nanoscale device design and modeling
  • Beyond CMOS
  • Light Weight and Flexible High Performance Electronics
  • Device-circuit co-design
  • Electrothermal modeling
  • On-chip ESD Protection
  • Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT)
  • LDMOS and DeMOS HV/Power device design
  • Nanotechnology for Mobile Systems
  • Analog Memory for Neuromorphic applications

Research Highlights

Other than key contributions listed before. These areas were started at IISc from scratch

A. New Discovery yields a giant leap in graphene transistor performance: In a major breakthrough in the field of graphene based electronics, my group has made a big jump in understanding the quantum nature of graphene’s interface with outside world. The team has studied how the overlap of atomic orbitals between Carbon and metal atoms affects the graphene-metal interface. The study has enabled to invent novel techniques to engineer graphene contact that has the lowest recorded contact resistance. As a result of this discovery and subsequent inventions, while breaking several records – including the one from IBM’s research centre in T. J. Watson, USA – it has eventually allowed achieving the highest graphene transistor performance.

B. Deeper insights into Electron-Phonon Transport Probed at nano-second time scale: We have developed a new technique to probe electron – phonon interaction at nano-second time scales. The idea is to isolate carrier transport from external or induced perturbations, which develop as a function of time, example phonon bath, and systematically study dynamics of electron transport. This is the first time any research group has developed and reported such a technique. Using this method we have reported, for the first time, (i) remote joule heating of cold contact and its impact on carrier transport through 1D and 2D materials, (ii) time constant of contact and channel annealing, (iii) dynamics of thermal failure and (iv) changeover from ballistic to diffusive transport attributed to scattering induced phonon bath at the nanosecond time scale.

C. Breakthrough in Nanometer scale transistor technology: My group has demonstrated a new transistor design which can significantly improve the chip performance and it’s scalability beyond 10nm technology node. It works at lower voltages, draws 15 times less charge in idle state and offers higher frequency performance. These factors ensure longer battery life, smaller chip area (lighter), lower cost and higher speed. This new device is expected to reduce chip cost by four to five times for IoT applications when compared to current day technology. In simple terms it offers a newer technology which is cheaper and can be manufactured without putting capital, that is newer manufacturing plants, and at the same time it offers significantly better performance and scalability.

D. New Class of Integrated Power Transistors: For the first time, a novel Drain extended tunnel FET device (DeTFET) is disclosed, while addressing need for high voltage / high power devices for System on Chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunnelling and associated carrier injection. Device’s intrinsic (DC/switching), analog and RF performance compared with state of the art drain extended NMOS device (DeNMOS) shows that the proposed device offers 15× better subthreshold slope, 8× lower OFF state leakage, 2× higher ON current, absence of channel length modulation and drain induced barrier lowering, while keeping 2.5× lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain and better RF characteristics, when compared to the DeNMOS device. The patented (and later published) device is expected to improve the performance of future power ASICs.

E. Nanoscale power electronic system-on-chip: Have come-up with a novel scheme for miniaturized integrated power electronic systems. This invention, which brings different power electronic components into a nano sized chip, which can potentially create new possibilities in the consumer electronic industry example phone charger and LED applications. This invention uses state of the art in different branches of nano-electronics, material technology and 3D integration and relies on recent technological developments like the wide bandgap power transistors, 3D integration, super capacitors, super inductors, graphene and carbon nano tubes. This invention can potentially influence a multi-billion dollar industry.

F. ESD reliability of newer material based transistor technologies: ESD is considered to be one of the most fundamental reliability issue associated with semiconductors. We have explored ESD reliability of graphene and CNT like 1D and 2D material based devices and GaN based high electron mobility transistors. My group has published majority of papers in this field.

G. Performance and reliability advancement of LDMOS devices: It’s been over 40 years when the first power MOSFET was invented. However, till the recent years, performance and reliability of these devices was considered to independent phenomena and was always studied / addressed independently. In our recent works, for the first time, we have attempted to find common design knobs to tackle both the challenges. In this direction, we have (i) unified physics of quasi-saturation in power MOSFETs, which was considered to be a fundamental bottleneck; (ii) using the unified physics we have shows different ways by which quasi-saturation can be mitigated, which improves device performance and (iii) have come-up with few design proposals, which improves the device performance as well as reliability. These recent works are expected to change the way power MOSFETs were designed and used in integrated circuits.

Funding and Sponsors

So. No.

Project Title

Agency

Value in Rs. (Lacs)

Duration

PI/Co-PI/Investigator

1

Institute Seed Grant for the Establishment of Advance Nanoelectronic Device & Circuit Research Laboratory

IISc

34

Oct 2013 – Sep 2014

PI

2

Demonstration of Graphene based RF Transistors

DRDO (SSPL)

10

June 2014 – Oct. 2014

PI

3

Exploration of Carrier Transport and Contact Resistance Behaviors in Carbon Nanotube and Graphene Devices Using Nanosecond Time Scale Charge Bust

DST (SERB)

51.7

July 2014 – June 2017

PI

4

Investigation on GaN devices for power electronic switching applications and design and development of a high frequency GaN convertors topology

NaMPET Phase-II

191.2

Oct. 2014 – March 2017

Investigator

5

Advance Nanoscale Characterization Facility

IISc

110.1

Jan 2015 – Sep 2015

PI

6

ESD Reliability of sub-14nm node technologies

Intel, Germany

100

Dec 2015 – Nov. 2018

PI

7

12th Plan Grant to Develop Laboratory Space

IISc

5

Sep 2016 – March 2017

PI

8

Technology Development for 600V Normally – OFF Gallium Nitride Transistor for Reliable Power Electronic Systems

DST (TSDP)

1028

May 2016 – April 2019

PI

9

Graphene Based THz Transistor Technology

DRDO (ERIPR)

470

Dec 2016 – Nov. 2010

PI

10

High Voltage & ESD Device Development & Enablement in SCL’s 180nm CMOS Technology

IMPRINT

300

Jan 2017 – June 2019

PI

11

Detailed Project Report on a Commercial GaN Foundry

DeitY

60

March 2016 – Sep. 2016

Investigator

Total Sanctioned Funding Till Nov. 2016

2360

Facility
  1. Wafer level High Power Device Characterization setup
  2. Wafer level low current and low temperature Characterization setup
  3. ESD Characterization setup (TLP and vf-TLP)
  4. Setup for nano-material transfer/deposition
  5. Nano-second pulse characterization setup
  6. Stamping stage with high resolution microscope and nano positioners for 2D material transfer and stacking
  7. High end computational clusters with total 96 cores
  8. An integrated EL/PL/Raman system with low temperature (Liquid N2) sample mounting/probing stage
  9. Fully automated low temperature probe station
  10. Automated semiconductor device reliability characterization setup
  11. Wafer level ultra high power measurement setup
  12. Wafer level – automated – low current (down to fA) / low power device characterization setup
  13. Setup for thermal conductivity and diffusivity characterization of 2D materials and thin films
  14. Setup for 1/f noise characterization in 2D material systems
  15. 67 GHz PNA
  16. HBM tester
  17. CCR based sub-1k probe setup
  18. Range of laser sources
  19. Load-pull setup for RF power amplifier / power device characterization
Research Group
  • 12 PhD students at present (6 # Nanoelectronics, 3 # Power/HV devices & 3 # ESD reliability). 2 of these PhD students were earlier my ME students, 5 have M-Tech degrees from some of the good schools in India and remaining 5 are among the top 500 gate rankers who joined after B-Tech.
  • 1 # M-Tech student (Nano) & 7 # JRF/SRF (2 Nano, 5 Power/HV)
  • Most of the students get following expertise: Mix of semiconductor device processing, device / material characterization, computation, modeling and theory
  • Projected headcount by Q2/Q3-2017: 15 PhD + 12 JRF/SRF/PDF

PhD Students

1. Adil Meersha (PhD)

2. Abhishek Mishra (PhD)

3. Milova Paul (PhD)

4. Harsha B (PhD)

5. Sampath B (PhD)

6. Kranthi N. K. (PhD)

7. Ankit Soni (PhD)

8. Hemanjaneyulu Kuruva (PhD)

9. Bhawani Shankar (PhD)

10. Satyajith B (PhD)

11. Ansh (PhD)

12. Rajat Sinha (PhD)

Teaching and Workshops

Courses Taught:

So. No.

Course Code: Course Title

1

EP301: Independent Research Study

2

E3-271: Reliability of Nanoscale Circuits and System

3

E3-272: Advanced ESD devices, circuits and design methods

4

E3-274: Power Semiconductor Devices and Physics

What is so unique about these courses: There is no standard text book for these courses. Instructor has designed these courses from his industry experiences. It is worth highlighting that except 2-3 universities worldwide, no university in the world (to the best of instructor’s knowledge) offers a comprehensive course on semiconductor reliability (E3-271) and power semiconductor devices (E3-274), respectively. Uniqueness of these courses (E3-271 and E3-274) is that they are heavy in device design concepts, however deals minimum with mathematics, which trains students to work independently on real world device design problems.

Workshop Hosted:

  • 2nd India ESD Workshop: This was the second edition of India ESD workshop, as part of India ESD forum formed in year 2016. This time it was much more professionally organized with over 80 registrations. The event is going to be covered by ESD Association’s (USA) newsletter, IEEE EDS newsletters, as well as several online media houses, which are published internationally.
  • ESD Design Essentials: 2 day workshop hosted at Hotel Oberoi, Bangalore. This was technically and financially sponsored by ESDA, USA.
  • 1st India ESD Workshop: 1 day workshop on on-chip ESD design, hosted in IISc. Single-handedly formed a forum or nationwide special interest group called “India ESD Forum”, which today has over 60 industry members. This workshop was attended by over 30 industry senior engineers / managers. The event was covered by ESD Association’s (USA) newsletter, which is published internationally.
  • Offered a 3 day ESD course / workshop to X-Fab engineers in Kuching, Malaysia. This was fully funded by X-Fab and was registered by over 25 X-Fab engineers.
Recognitions

Professional Recognitions, Awards, and Fellowships:

  1. 2015 IEEE EDS Early Career Award, one of the highest honours given by IEEE Electron Device Society (EDS).
  2. IEEE Senior Member (since August 2016)
  3. Department of Electronics & Information Technology (DeitY), Govt. of India, Young Faculty Fellowshipfor the duration of 2016 – 2020.
  4. India TR35, 2010, Young Innovator Award. Technology Review’s TR35 list by Massachusetts Institute of Technology recognizes the outstanding innovators under the age of 35 each year. Received on March 8, 2010
  5. Award for Excellence in Thesis Work, IIT Bombay-2010, received on 6th August, at the 48th convocation of IIT Bombay.
  6. IIT Bombay – Industrial Impact Award, for pursuing research work that caused maximum industry impact. Received on September 6, 2010
  7. Outstanding Paper Award, VLSI Design Conference, Jan. 2017
  8. Best Research paper Award, Intel Asia Academic Forum 2008, Oct 2008, Taipei, Taiwan.
  9. 2000 Outstanding Intellectuals of the 21st Century-2010 – Biography publication by International Biographical Center (IBC), Cambridge, England
  10. Infineon Fellowship, Duration: November 2008- July 2010
  11. Technical Program Committee (TPC)
    1. IEEE International Reliability Physics Symposium, USA 2017
    2. EOSESD symposium, USA: 2012 – 2017 (Sub-committee chair in 2014 & 2017)
    3. IEEE VLSI Design 2011, 2014, 2015 (Vice-chair, “Device and Process Technology” session)
    4. IEEE ESSDERC, Europe: 2014 – 2016
    5. IWPSD 2015 and 2017
  12. Editor for Electronic Devices and Components of IETE Journal of Research
  13. Reviewer for several journals including JJAP, MR, IEEE T-ED, IEEE EDL and IEEE TDMR
    1. Listed 7 times (2009, 2010, 2012 – 2016) in the IEEE T-ED golden list of reviewers
    2. Listed 4 times (2012 – 2015) in the IEEE EDL golden list of reviewers
Press Coverage
Invited Talks

Invited Talks (Other than peer reviewed presentations)

  1. The Future of Electronics
    1. 51st Computer Society of India Conference (Memorial Talk, Jan. 24th 2016)
    2. IEEE Golden Jubilee Congress (August 2016)
    3. IISc EECS Symposium (Feb 2016)
  2. Gallium Nitride Electronics: Design and Reliability“, ICYRAM-2016, Dec. 14th 2016
  3. Record High Graphene Transistor Performance
    1. IEEE International Conference on Emerging Electronics, Dec. 27th 2016
    2. IIT Delhi, Jan 9th 2017
    3. IIT Kanpur, Jan 10th 2017
  4. “On Chip ESD Design: Why EDA Based Approach is Becoming Important?”, Key Note talk at Cadence India Design Center, Dec 11th 2015
  5. “How to Design Si High Voltage and Power Devices”, Semiconductor Complex Limited (SCL), Department of Space, July 2nd 2015
    1. Semiconductor Complex Limited (SCL), Department of Space, July 2nd 2015
    2. ANURAG, DRDO, Feb 2017
  6.  “On-Chip ESD Devices and Circuits: Essentials and Research Opportunities
    1. 2nd India ESD Workshop, March 17th, 2017
    2. ANURAG, DRDO, Feb 2017
    3. 1st India ESD Workshop, Feb 26th, 2016
    4. IIT Gandhinagar, Dec. 31st 2015
    5. Semiconductor Complex Limited (SCL), Department of Space, July 1st 2015
    6. EE Department, IIT Madras, July 2014
    7. Texas Instruments Bangalore, India, April 2014
    8. CRL Bangalore, Feb. 2014
    9. Fifth Electrical Sciences Symposium, IISc Bangalore, Feb. 2014
  7.  “ESD Design Essentials”, Bangalore, 8th and 9th Jan. 2015
    1. ESD Device Physics
    2. On-Chip ESD (Circuit) Design
    3. CDM Phenomena and Protection Design
    4. Latch-up
  8. “How to Design GaN HEMT Devices”, International conference on Emerging Electronics, Dec. 5th 2014
  9. ESD Robust LDMOS Design Essentials” Online webinar organized by ESD Association USA, telecasted globally in Nov. 2014.
  10.  “IC and System Design for Electrostatic Discharge Protection“, IEEE INDICON, Dec. 2013
  11. Drain extended MOS device design and reliability challenges” IWPSD Dec. 2013
  12. A Review on the ESD Robustness of Drain Extended MOS Devices” International ESD workshop, May 20, 2013, Warrenton, VA, USA
  13. 3D TCAD Based approach for ESD failure analysis“, Infineon Technologies, AG, Munich (Germany), June 2010.
  14. Reliability aware I/O design for sub 45nm node CMOS technology” IWPSD-2009, 18th Dec, 2009.
  15. Benchmarking the device performance at sub 22 nm node technologies using an SoC framework“, IWSG-2009, 3rd Dec 2009.
  16. 3D filament behavior of various HV DeMOS devices under ESD condition” University of California (SB), USA, 4th Sep, 2009.
  17. Filament behavior of various DeMOS devices“, Technical University of Vienna, Austria, 8th Oct 2008.
  18. ESD optimization of DeMOS devices“, Infineon Technologies, AG, Munich (Germany), 6th Oct 2008.
  19. Mixed signal and hot carrier performance of various DeMOS devices” Infineon Technologies, AG, Munich (Germany), 3rd May 2008.
Patents

Granted/Issued (United States Patent Office):

  1. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei,” Semiconductor devices with trench isolations”, United States Patent (2012) 8,097,930
  2. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “Operational Amplifier Having Improved Slew Rate ” United States Patent (2012) 8,089,314
  3. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Nonvolatile floating gate analog memory cell”, United States Patent (2013) 8,436,413
  4. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (2013) 8,354,710
  5. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, Ramgopal Rao, Christian Russ, “Device and method for coupling first and second device portions”, United States Patent (2013) 8,455,947
  6. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (2013) 8,536,648
  7. Mayank Shrivastava and Harald Gossner, “Drain extended MOS device for Bulk FinFET technology”, United States Patent (2014) 8,629,420
  8. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Semiconductor devices and methods for manufacturing a semiconductor device”, United States Patent (2014) 8,643,090
  9. Mayank Shrivastava, Christian Russ, Harald Gossner, “Low voltage ESD clamping using high voltage devices”, United States Patent (2014) 8,654,491
  10. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (2014) 8,664,720
  11. Mayank Shrivastava, Christian Russ, Harald Gossner, “Selective current pumping to enhance low-voltage ESD clamping using high voltage devices”, United States Patent (2014) 8,681,461
  12. Mayank Shrivastava and Harald Gossner, “Silicon controlled rectifier (SCR) device for bulk FinFET technology”, United States Patent (2015) 8,785,968
  13. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable Fin-SCR for Robust ESD Protection”, United States Patent (2015) 8,963,201
  14. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-Effect Device and Manufacturing Method Thereof”, United States Patent (2015) 9,035,375
  15. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain Extended Field Effect Transistors and Methods of Formation Thereof”, United States Patent (2015) 9,087,892
  16. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements for electrostatic (ESD) protection”, United States Patent (2016) 9,356,013
  17. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, Ramgopal Rao, “Methods for manufacturing a semiconductor device”, United States Patent (2016) 9,368,573
  18. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (2016) 9,401,352
  19. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (2016) 9,455,275

Published/Patent Pending (United States Patent Office):

  1. Mayank Shrivastava and Christian Russ, “FinFET and Fin-BJT SCR as ESD clamp with Built-In trigger circuit and Current Ballasting mechanism including Checker-Board Layout Technique for Uniform SCR Turn-On”, United States Patent (2015) 20150008476.
  1. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable FIN-SCR for Robust ESD Protection”, United States Patent (2015) 20150144997.
  2. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements for electrostatic discharge protection”, United States Patent (2016) 20160240525.
  3. Christian Russ, Mayank Shrivastava and Markus Schwiegershausen, “Transient-Triggered SCR for FinFET Technology (FF-TTSCR) for ESD Protection of RF IO”, United States Patent pending (Filed August 2015).

Filed (Indian Patent Office):

  1. Milova Paul, Mayank Shrivastava, Sampath Kumar, Christian Russ and Harald Gossner, “Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device”, Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017
  2. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Non-planar Electrostatic Discharge (ESD) Protection Devices With Nano Heat Sinks”, Indian Patent, Application No 201741003773, Filed on 1st Feb. 2017
  3. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Low Trigger And Holding Voltage Silicon Controlled Rectifier (SCR) For Non-Planar Technologies”, Indian Patent, Application No 201741003772, Filed on 1st Feb. 2017
  4. Mayank Shrivastava, Milova Paul and Harald Gossner, “Fin FET SCR With SCR Implant Under Anode And Cathode Junctions”, Indian Patent, Application No 201741006746, Filed on 25th Feb. 2017
  5. Mayank Shrivastava, Milova Paul and Harald Gossner, “Electrostatic Discharge (ESD) Protection Devices For ESD Robustness And Latch-Up Immunity”, Indian Patent, Application No 201741006745, Filed on 25th Feb. 2017
  6. Mayank Shrivastava, “Drain extended Tunnel FET”, Patent Application No: 201641006497, Filed on Feb 26th 2016.
  7. Mayank Shrivastava and Kuruva Hemanjaneyulu “Fin enabled area scaled tunnel field Effect transistor”, Patent Application No: 2625/CHE/2015, Filed on May 26th 2015.
  8. Mayank Shrivastava, “Miniaturized, High Power Density Power Electronic System on a Chip”, Patent Application No: 1355/CHE/2015, Filed on March 19th 2015.
  9. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Independently Driven Double Gate (IDDG) Nonvolatile floating gate analog memory cell”, Indian Patent pending, 2008, Patent Application No 2217/MUM/2008, Filed on 15th October 2008.
  10. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, ” A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, Patent Application No 542/MUM/2010, Filed on 2nd March 2010.

Under Filing (Indian Patent Office):

  1. N. S. Kranthi and Mayank Shrivastava, “ESD Robust Tunnel FET Device”, Pending for Indian patent filing
  2. Mayank Shrivastava, “GaN HEMT Device with high Breakdown Voltage”, Pending for Indian patent filing
  3. Mayank Shrivastava, “Heterogeneous Junction GaN HEMT Device”, Pending for Indian patent filing
  4. Mayank Shrivastava, “GaN HEMT device with improved gate control and higher breakdown voltage”, Pending for Indian patent filing
Publications

Publications in the IEEE International Electron Devices Meeting (IEDM) & the IEEE International Reliability Physics Symposium (IRPS) (the two most prestigious conferences for Electron Devices): 13

Books, Book chapters and Technical Briefs

  1. Chapter titled “Towards Drain extended FinFETs for SoC applications” in book “Toward Quantum FinFET”, edited by Weihua Han and Zhiming M. Wang, Springer, Dec. 2013, ISBN 978-3-319-02021-1.
  2. Mayank Shrivastava and V. Ramgopal Rao, “Tunnel Field Effect Transistors”, Present, Past and Future, Technical Brief appeared in the IEEE EDS Newsletters, July 2016 (Cover page article).

Journals

  1. Abhishek Mishra and Mayank Shrivastava, “Remote Joule Heating Assisted Carrier Transport in MWCNTs Probed at Nanosecond Time Scale”, Journal of Royal Society of Chemistry, 2016,18, 28932-28938 (DOI: 10.1039/C6CP04497B).
  2. Mayank Shrivastava, “Drain Extended Tunnel FET – A Novel High Voltage Device for Beyond FinFET System on Chip & Automotive Applications”, to appear in IEEE Transactions on Electron Devices
  3. Vipin Joshi, Ankit Soni, Shree Prakash Tiwari and Mayank Shrivastava, “Computational Modeling Strategy for AlGaN/GaN HEMT Systems”, IEEE Transactions on Nanotechnology, Nov. 2016
  4. Kranthi Nagothu and Mayank Shrivastava, “On the ESD Behavior of Tunnel FET Devices”, to appear in IEEE Transactions on Electron Devices
  5. Kuruva Hemanjaneyulu and Mayank Shrivastava, “Fin Enabled Area Scaled Tunnel FET”, IEEE Transactions on Electron Devices, Vol. 62, No. 10, Oct. 2015
  6. Mayur Ghatge and Mayank Shrivastava, “Physical Insights On the Ambiguous Metal Graphene Interface and Proposal for Improved Contact Resistance”, IEEE Transactions on Electron Devices, Vol. 62, No. 12, Dec 2015
  7. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, Harald Gossner, and V. Ramgopal Rao, “On the Improved High-Frequency Linearity of Drain Extended MOS Devices”, IEEE Microwave and Wireless Components Letters, Volume: 26, Issue: 12, Dec. 2016
  8. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain Extended PMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, No. 12, Dec 2015
  9. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, No. 12, Dec 2015
  10. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part II: A Fully Integrated RF PA in 28nm CMOS with Device Design for Optimized Performance and ESD Robustness”, IEEE Transactions on Electron Devices, Vol. 62, No. 10, Oct. 2015
  11. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part I: High Voltage MOS Device Design for Improved Static and RF Performance”, IEEE Transactions on Electron Devices, Vol. 62, No. 10, Oct. 2015
  12. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “On the Geometrically Dependent Quasi-Saturation and gm Reduction in Advanced DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 63, No. 4, April 2016.
  13. Mayank Shrivastava, Neha Kulshrestha and Harald Gossner, “ESD Investigations of Multiwalled Carbon Nanotubes”, IEEE Transactions on Device and Material Reliability, Vol. 14, No. 1, March, 2014, pp: 555 – 563.
  14. Peeyush Swain, Mayank Shrivastava, Harald Gossner, M. S. Baghini and V. Ramgopal Rao, “Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 11, November, 2013, pp: 3827-3834.
  15. B Sampath Kumar and Mayank Shrivastava, “Part I: On the Unification of Physics of Quasi-Saturation in LDMOS Devices”, to appear in IEEE Transactions on Electron Devices (after mandatory revision)
  16. B Sampath Kumar and Mayank Shrivastava, “Part II: Correlation Between Quasi Saturation and RF, ESD, Hot Carrier Degradation, Self Heating and Safe Operating Area Concerns”, to appear in IEEE Transactions on Electron Devices (after mandatory revision)
  17. Bhawani Shankar and Mayank Shrivastava, “Part-I: Unique ESD Behavior of AlGaN/GaN HEMTs”, Submitted to IEEE Transactions on Electron Devices
  18. Bhawani Shankar and Mayank Shrivastava, “Part-II: New Physical Insight into Unique Failure modes of AlGaN/GaN HEMTs under ESD Conditions”, Submitted to IEEE Transactions on Electron Devices
  19. Jhnanesh Somayaji, B.Sampath Kumar, M. S. Bhat, Mayank Shrivastava, “On the Device Design Guideline, Switching/RF Performance and HCI/ESD Reliability of Non-Conventional Drain extended MOS Devices for Advanced SoC Applications”, Submitted to IEEE Transactions on Electron Devices
  20. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Revisited”, Submitted to IEEE Transactions on Electron Devices
  21. Abhishek Mishra and Mayank Shrivastava, “Nano-Second Time Resolved High field Transport through Multi-walled Carbon Nanotube”, submitted to Applied Physics Letters
  22. Ankit Soni, Vipin Joshi, Shree Prakash Tiwari and Mayank Shrivastava, “Device Design Guidelines for AlGaN/GaN HEMT System”, Submitted to IEEE Transactions on Nanotechnology
  23. Kuruva Hemanjaneyulu and Mayank Shrivastava, “Air Stable and Cost Effective Doping of MoS2 FETs using KI Solution”, Submitted to ACS Nano
  24. Abhishek Mishra, Adil Meersha, Srinivasan Raghavan and Mayank Shrivastava, “Observing Non-equilibrium State of Transport through Graphene Channel at the Nano-Second Time Scale”, Submitted to ACS Nano
  25. Anukool Rajoriya, Mayank Shrivastava, Harald Gossner, Thomas Schulz and V. Ramgopal Rao “Sub 0.5V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET Devices”, IEEE Transactions on Electron Devices, Volume: 60, Issue: 8, August, 2013, pp: 2626-2633.
  26. Mayank Shrivastava and Harald Gossner, “A Review on the ESD Reliability of Drain Extended MOS Devices”, IEEE Transactions on Device and Material Reliability, Vol. 12, Issue 4, December, 2012, pp: 615-625. (Invited Review Paper)
  27. Mayank Shrivastava, Harald Gossner and V. Ramgopal Rao, “A Novel Drain Extended FinFET Device for High Voltage High Speed Applications”, IEEE Electron Device Letters, Vol. 33, Issue: 10, October, 2012, pp: 1432-1434.
  28. Mayank Shrivastava, Harald Gossner and Christian Russ, “A Novel Drain Extended NMOS Device with Spreading Filament under ESD Stress”, IEEE Electron Device Letters, Vol. 33, Issue: 9, September, 2012, pp: 1294-1296
  29. Mayank Shrivastava, Manish Agrawal, Sunny Mahajan, Harald Gossner, Thomas Schulz, Dinesh Kumar Sharma, and V. Ramgopal Rao, “Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures”, IEEE Transactions on Electron Devices, Volume: 59, Issue: 5, May, 2012, pp: 1353-1363.
  30. Mayank Shrivastava, Ruchit Mehta, Shashank Gupta, M. Shojaei Baghini, D. K. Sharma, Harald Gossner, T. Schulz, K. Arnim, W. Molzer, V. Ramgopal Rao, “Towards System On Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines”, IEEE Transactions on Electron Devices, Volume: 58, Issue: 6, June, 2011, pp: 1597-1607.  (This paper is recognized as feature article in Synopsys newsletter, May 2011)
  31. Ram Asra, Mayank Shrivastava, K. V. R. M. Murali, R. K. Pandey, Harald Gossner and V. Ramgopal Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance”, IEEE Transactions on Electron Devices, Volume: 58, Issue: 7, July, 2011, Pages: 1855-1863.
  32. Rajesh A. Thakker, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, and Mahesh B. Patil, ” A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, Microelectronics Journals, Volume 42, Issue 5, May, 2011, Pages 758–765.
  33. Mayank Shrivastava, Ruchil Jain, M. Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Solution towards the OFF state degradation in Drain extended MOS device”, IEEE Transactions on Electron Devices, Volume: 57, Issue: 12, December, 2010, pp: 3536-3539.
  34. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar”, IEEE Transactions on Electron Devices, Volume: 58, Issue: 2, February, 2011, pp: 309 – 317.
  35. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II(Two-Dimensional Study-Biasing & Comparison With NMOS)”, IEEE Transactions on Electron Devices, Vol. 58, No. 2, February, 2011, pp: 318 – 326.
  36. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part I: On the Behavior of STI-Type DeNMOS Device under ESD Conditions”, IEEE Transactions on Electron Devices, Volume: 57, Issue: 9, September 2010, pp; 2235 – 2242.
  37. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions”, IEEE Transactions on Electron Devices, Volume: 57, Issue: 9, September 2010, pp: 2243 – 2250.
  38. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “A novel bottom spacer FinFET structure for improved power-delay & short channel performance”, IEEE Transactions on Electron Devices, Volume: 57, Issue: 6, June 2010, pp: 1287-1994.
  39. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART I-“Mixed Signal Performance of Various High Voltage Drain Extended MOS devices” IEEE Transactions on Electron Devices, Volume: 57, Issue: 2, Feb 2010, pp: 448-457.
  40. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART II-“A Novel scheme to optimize the mixed signal performance and hot carrier reliability of Drain Extended MOS devices” IEEE Transactions on Electron Devices, Volume: 57, Issue: 2, Feb 2010, pp: 458-465.
  41. Mayank Shrivastava, Maryam Shojaei Baghini, A. Sachid, Dinesh Kumar Sharma, V. Ramgopal Rao, “A Novel and Robust Approach for Common Mode Feedback using IDDG FinFET”, IEEE Transactions on Electron Devices, Volume: 55, Issue: 11, Nov 2008, pp: 3274-3282.

Peer Reviewed Conferences

  1. Adil Meersha, Harsha B Variar, Krishna Bharadwaj, Abhishek Mishra, Srinivasan Raghavan, Navakanta Bhat and Mayank Shrivastava, “Record Low Metal – (CVD) Graphene Contact Resistance Using Atomic Orbital Overlap Engineering”, Proceedings of IEEE International Electron Device Meeting, Dec. 5th – Dec. 7th, San Francisco, CA, USA, 2016
  2. N. K. Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene RF Transistors: Physical Insights and Technology Implications”, Proceedings of IEEE International Reliability Physics Symposium, USA, April 4th – April 6th, 2017
  3. Bhawani Shankar,……., Mayank Shrivastava, “Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, Proceedings of IEEE International Reliability Physics Symposium, USA, April 4th – April 6th, 2017
  4. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner, Mayank Shrivastava, “FinFET SCR: Design Challenges and Novel Fin SCR Approaches for On-Chip ESD Protection”, Proceedings of EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA
  5. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Nagaboopathy Mohan, Navakant Bhat, Srinivasan Raghavan and Mayank Shrivastava1, “On the ESD Behavior of AlGaN/GaN Schottky Diodes and Trap Assisted Failure Mechanism”, Proceedings of EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA
  6. Rajat Sinha, N.K. Kranthi, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of Pentacene Channel Organic Thin Film Transistor”, Proceedings of EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA
  7. Abhishek Mishra and Mayank Shrivastava, “Unique Current Conduction Mechanism through Multi Wall CNT Interconnects under ESD Conditions”, Proceedings of EOSESD Symposium, Anaheim, CA, USA, 11th – 14th September, 2016
  8. Abhishek Mishra and Mayank Shrivastava, “New Insights on the ESD Behavior and Failure Mechanism of Multi Wall CNTs”, Proceedings of IEEE International Reliability Physics Symposium, Pasadena, CA, USA, 17th – 19th April, 2016
  9. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior and Failure Modes of AlGaN/GaN HEMTs”, Proceedings of IEEE International Reliability Physics Symposium, Pasadena, CA, USA, 17th – 19th April, 2016
  10. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 (Received outstanding research paper award)
  11. Bhawani Shankar and Mayank Shrivastava, “ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017
  12. Adil Meersha, Sathyajit B and Mayank Shrivastava, “A Systematic Study on the Hysteresis Behavior and Reliability of MoS2 FET”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017
  13. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Device-Circuit Co-design for High Performance Level Shifter by Limiting Quasi-saturation Effects in Advanced DeMOS Transistors”, IEEE INEC, 9th – 11th, May, 2016, China
  14. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology mounted in BGA Package”, Proceedings of IEEE VLSI Design Conference, Jan. 2016
  15. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “On the Breakdown Physics of Trench-Gate Drain Extended NMOS”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore.
  16. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “Comparison of Breakdown Characteristics of DeNMOS Devices with Various Drain Structures”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore.
  17. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Drain Extended MOS Device Design for Integrated RF PA in 28nm CMOS with Excellent FoM and ESD Robustness”, Proceeding of IEEE International Electron Device Meeting (IEDM) Dec. 2014, San Francisco, CA, USA.
  18. Mayank Shrivastava and Harald Gossner, “ESD Behavior of Metallic Carbon Nanotubes”, Proceedings of 36th EOSESD Symposium, 7th – 12th Sep. 2014, Tucson, Arizona, USA.
  19. Mayank Shrivastava, Christian Russ, Harald Gossner, S. Bychikhin, D. Pogany and E. Gornik, “ESD Robust DeMOS Devices in Advanced CMOS Technologies”, Proceedings of EOSESD symposium, 11th – 15th Sep. 2011, Anaheim, California, USA.
  20. Junjun Li, Rahul Mishra, Mayank Shrivastava, Yang Yang, Robert Gauthier, Christian Russ, “Technology Scaling Effects of Silicide-blocked PMOSFET Devices under ESD like conditions in Advanced Nanometer Node Bulk CMOS Technologies”, Proceedings of EOSESD Symposium, 11-15 Sep. 2011, Anaheim, California, USA.
  21. Mayank Shrivastava, Christian Russ, Harald Gossner, “On the Impact of ESD Implant and Filament Spreading in Drain extended NMOS devices”, International ESD Workshop, May 2011, Lake Tahoe, CA, USA.
  22. Mayank Shrivastava, Manish Agrawal, Jasmin Aghassi, Harald Gossner, Wolfgang Molzer, Thomas Schulz, V. Ramgopal Rao, “On the thermal failure in nanoscale devices: Insight towards Heat Transport and Design Guidelines for Robust Thermal Management & EOS/ESD Reliability”, Proceedings of IEEE International Reliability Physics Symposium, 10-14 April, 2011, Monterey, CA, USA.
  23. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “On the Transient Behavior of Various Drain Extended MOS Devices under the ESD stress conditions”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited)
  24. Saurabh Nema, Mayank Shrivastava, Angada B. Sachid, A. K. Saxena, Anand Bulusu, “A Novel Scaling Strategy for Underlap FinFETs”, ICCCD, India, 2010
  25. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “3D TCAD based approach for the Evaluation of Nanoscale Devices during ESD Failure”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited)
  26. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA.
  27. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “On the differences between 3D filamentation and failure of n & p type drain extended MOS devices under ESD condition”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA.
  28. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Reliability aware I/O design for sub 45nm node CMOS technology”, IWPSD-2009, 15th -19th Dec, 2009 (Invited).
  29. Mayank Shrivastava, Bhaskar Verma, M. Shojaei Baghini, Christian Russ, Dinesh K. Sharma, Harald Gossner, V. Ramgopal Rao, “Benchmarking the Device Performance at sub 22 nm node Technologies using an SoC Framework”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA.
  30. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “Filament Study of STI type Drain extended NMOS device using Transient Interferometric Mapping”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA.
  31. Mayank Shrivastava, Jens Schneider, Ruchil Jain, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “IGBT plugged in SCR device for ESD protection in advanced CMOS technology”, Proceedings of EOS/ESD symposium, August 30th – September 4th, 2009, Anaheim, CA, USA.
  32. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “Highly resistive body STI: n-DEMOS: An optimized DEMOS device to achieve moving current filaments for robust ESD protection”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada.
  33. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “A New Physical Insight and 3D Device Modeling of STI Type DENMOS Device Failure under ESD Conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada.
  34. A. B. Sachid, Mayank Shrivastava, R. A. Thakkar, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Asia Academic Forum 2008, Oct. 20th – Oct. 22nd 2008, Taipei, Taiwan. (Received the best research paper award).