Prof. Mayank Shrivastava
Associate Professor
Department of Electronic Systems Engineering
Indian Institute of Science Bangalore, 560012
E-mail: mayank@iisc.ac.in
Contact: +91-80-2293-2732

Education
Ph. D. in Electrical Engineering (2010), Indian Institute of Technology Bombay, Mumbai, India
B.E. in Electronics and Communication (2006), Rajiv Gandhi Technical University, Bhopal

Bio & Key Contributions

Achievements: Prof. Mayank Shrivastava received his PhD degree from Indian Institute of Technology Bombay. For his PhD work he received excellence in research award for his PhD thesis in 2010 and industrial impact award from IIT Bombay in 2008. He is among the first recipients of Indian section of American TR35 award (2010) and the first Indian to receive IEEE EDS Early Career Award (2015). Besides, he is an IEEE Senior Member and has received several other national awards and honors of high repute, like National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018; Indian National Academy of Science (INSA) Young Scientist Award – 2018; Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation); Indian National Academy of Engineering (INAE) Young Engineer Award – 2017; INAE Young Associate (since 2017); Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023; Department of Electronics & Information Technology (DeitY), Young Faculty Fellowship.  He has received best paper awards from several international conferences like Intel Corporation Asia academic forum; VLSI design conference and EOSESD Symposium. Prof. Shrivastava’s current research deals with experimentation, design and modeling of beyond CMOS devices using Graphene and TMDCs, wide bandgap material-based power semiconductor devices and ESD reliability in advanced and beyond CMOS nodes. He had held visiting positions in Infineon Technologies, Munich, Germany from April 2008 to October 2008 and again in May 2010 to July 2010. He worked for Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; and Intel Corp., Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined Indian Institute of Science as a faculty member in year 2013 where he is currently working as an Associate Professor. Prof. Shrivastava has over 110 peer reviewed international publications and 40 patents.

Contributions: Prof. Shrivastava’s one of the key contributions has been development, enablement and integration of nanoscale CMOS and power MOSFET devices in advanced CMOS nodes for System on Chip (SoC) applications. As his PhD work at IIT Bombay, which was later extended at Intel, he was instrumental in developing and enabling integrated power MOSFETs (LDMOS or DeMOS devices) for power management and RF modules, which in advance SoCs covers 40 – 50% of the chip area. In general, his innovations on integrated high power switching and RF devices has enabled the semiconductor industries in the system on chip integration [T-ED Feb. 2010, Part I & II] [United States Patents # 8643090, 8097930] [T-ED 2015, Part I & II]. For example, since 1970 various CMOS devices were proposed for integrated high power RF and switching applications. However, they used to fail under high current conditions, which seriously hampered the usefulness of these devices for advanced SoC products. The physical cause for such failures was not known to scientists before. Work done by Prof. Shrivastava provided a clear physical insight into the failure mechanism of Si power MOSFETs under extreme conditions [IEDM 2009] [IRPS 2009] [T-ED Sep. 2010 Part I & II] [IRPS 2010]. His investigations revealed the limiting factors associated with conventional power MOSFETs. Moreover, his work unified the various theories related to the failure mechanism in different type of high power devices. For example, various groups in the past speculated that failure in power MOSFETs is a random event; however Prof. Shrivastava’s work revealed deterministic and unified nature of these failures across various types of integrated power MOSFET devices. Going further, he used his theory and device insights to invent new class of robust & high performance power MOSFETs [United States Patents # 8536648 & 8354710] [IEDM 2014], which can be found in advanced SoC today. His research also changed the perception that robustness and performance cannot be achieved together, particularly for the high power-high frequency applications [T-ED Dec 2010]. Going a step further, he invented and designed first high power devices for FinFET technology [IEDM 2009] [EDL 2013] [United States Patents # 8664720 & 8455947] [IRPS 2018]. SoC design in these very advance CMOS technologies was not expected to take place in near future. However, recent device inventions resulted from Prof. Shrivastava’s work has enabled semiconductor industries for the design and manufacturing of SoC in FinFET and related CMOS nodes. As of now, Prof. Shrivastava holds over a dozen key LDMOS patents and most of the FinFET power MOSFET patents. These designs are used in current day system on chips.
At IISc Bangalore, these contributions of Prof. Shrivastava have led to indigenous power SoC development initiative jointly with SCL, which has resulted in a project funded by IMPRINT-I. Prof. Shrivastava’s efforts have resulted in indigenous development of LDMOS devices using SCL foundry, for strategic applications. Furthermore, extension of this work to other power semiconducting materials like Gallium Nitride in his group, as a result of a DST funded project led by him, has resulted in a record high performance e-mode GaN FET with over 25 international publications and 6 patents. These are being widely appreciated by semiconductor industries due to its usability. The technology at IISc Bangalore is ready to get scaled-up before its potential commercialization.
At the nanoelectronics front, Prof. Shrivastava has made major contributions towards next generation system on chips which involves novel device architectures, new materials and complex technology integration. In over 25 international publications including IEEE T-ED, IRPS and IEDM, his work has highlighted the device-circuit co-design approach involving FinFETs and tunnel FETs for mixed signal SoC applications. The FinFET design concepts proposed by him have been found useful for mobile phone applications. These concepts have helped improving the battery standby time while improving the performance. Moreover, these works have established a methodology for understanding the impact of the process & device design on the circuit performance and provided insights into the effect of device level design optimization & reliability improvement on the SoC performance. At IISc Prof. Shrivastava has extended these nanoelectronics activities to beyond Si materials, like Graphene, TMDCs and Phosphorene. RF FET technology developed at IISc Bangalore using CVD Graphene as channel material has broken past records including the best transistor performance reported by IBM T. J. Watson (USA) Center [IEDM 2016]. Prof. Shrivastava’s group has also developed a unique method to dope MoS2 for making contacts, which has led to significant improvement in transistor performance. Besides, Prof. Shrivastava’s group has also developed unique methods to enhance carrier injection across all TMD-metal interfaces and improve hole injection.

Work Experience

  1. Associate Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (June 2019 – Present).
  2. Assistant Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (September 2013 – May 2019).
  3. Staff Engineer: Intel Corp. (MCG), Munich, Germany (April. 2013 – August 2013).
  4. Senior Engineer: Intel Corp. (MCG), Munich, Germany (Sep. 2011 – March 2013).
  5. Senior Engineer: Infineon Technologies, USA (Sep 2010 to Jan 2011) and Intel Corp. (MCG), USA, (Feb 2011 to Sep 2011).
  6. Visiting Scholar: Infineon Technologies, Munich, Germany. April 2008 to Oct 2008 and again from May 2010 to July 2010.

Research Interest

Research Focus

My group works on the science and technology of electron devices, having focus on power semiconductor devices as well as nanoscale / beyond Si CMOS for SoC applications. Given a strong focus on the semiconductor technology for the future electronics, we also work on a multitude of science threads like (i) physics of semiconductor device reliability, (ii) electro-thermal / electron – phonon interaction in beyond Si materials / devices, (iii) thermometry and thermal / phonon transport in these materials / devices. Both the science and technology threads are briefed in figure below.

Research Interest and Thrust Areas

  • Graphene, Carbon Nanotubes and novel 1D/2D materials
  • Nanoscale device design and modeling
  • Beyond CMOS
  • Light Weight and Flexible High Performance Electronics
  • Device-circuit co-design
  • Electrothermal modeling
  • On-chip ESD Protection
  • Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT)
  • LDMOS and DeMOS HV/Power device design
  • Nanotechnology for Mobile Systems
  • Analog Memory for Neuromorphic applications

Research Highlights

1. Understanding quantum nature of graphene-metal contact yields a giant leap in graphene transistor performance

My group has made a big jump in understanding the quantum nature of graphene’s interface with outside world. The team has studied how the overlap of atomic orbitals between Carbon and metal atoms affects the graphene-metal interface. The study has enabled to invent novel techniques to engineer graphene contact that has the lowest recorded contact resistance. As a result of this discovery and subsequent inventions, while breaking several records – including the one from IBM’s research centre in T. J. Watson, USA – it has eventually allowed achieving the highest graphene transistor performance. This work was published in IEDM – 2016.

2. Deeper insights into Electron-Phonon Transport Probed at nano-second time scale

We have developed a new technique to probe electron – phonon interaction at nano-second time scales. The idea is to isolate carrier transport from external or induced perturbations, which develop as a function of time, example phonon bath, and systematically study dynamics of electron transport. This is the first time any research group has developed and reported such a technique. Using this method we have reported, for the first time, (i) remote joule heating of cold contact and its impact on carrier transport through 1D and 2D materials, (ii) time constant of contact and channel annealing, (iii) dynamics of thermal failure and (iv) changeover from ballistic to diffusive transport attributed to scattering induced phonon bath at the nanosecond time scale. (We have published these works at forums like IEEE T-ED, APL, IEEE IRPS, and EOSESD Symposium)

3. Breakthrough in Nanometer scale transistor technology

My group has demonstrated a new transistor design which can significantly improve the chip performance and it’s scalability beyond 10nm technology node. It works at lower voltages, draws 15 times less charge in idle state and offers higher frequency performance. These factors ensure longer battery life, smaller chip area (lighter), lower cost and higher speed. This new device is expected to reduce chip cost by four to five times for IoT applications when compared to current day technology. In simple terms it offers a newer technology which is cheaper and can be manufactured without putting capital, that is newer manufacturing plants, and at the same time it offers significantly better performance and scalability. This was published in IEEE T-ED.

4. New Class of Integrated Power Transistors:

For the first time, a novel Drain extended tunnel FET device (DeTFET) is disclosed, while addressing need for high voltage / high power devices for System on Chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunnelling and associated carrier injection. Device’s intrinsic (DC/switching), analog and RF performance compared with state of the art drain extended NMOS device (DeNMOS) shows that the proposed device offers 15× better subthreshold slope, 8× lower OFF state leakage, 2× higher ON current, absence of channel length modulation and drain induced barrier lowering, while keeping 2.5× lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain and better RF characteristics, when compared to the DeNMOS device. The patented (and later published in IEEE T-ED) device is expected to improve the performance of future power ASICs.

5. ESD reliability of newer material-based transistor technologies

ESD is considered to be one of the most fundamental reliability issue associated with semiconductors. We have explored ESD reliability of graphene, CNT, Pentacene and a-Si:H like new material-based devices and GaN based high electron mobility transistors. My group has published majority of papers in this field. (We have published these works at forums like IEEE T-ED, IRPS, ISPSD and EOSESD Symposium)

6. Performance and reliability advancement of LDMOS devices

It’s been over 40 years when the first power MOSFET was invented. However, till the recent years, performance and reliability of these devices was considered to independent phenomena and was always studied / addressed independently. In our recent works, for the first time, we have attempted to find common design knobs to tackle both the challenges. In this direction, we have (i) unified physics of quasi-saturation in power MOSFETs, which was considered to be a fundamental bottleneck; (ii) using the unified physics we have shown different ways by which quasi-saturation can be mitigated, which improves device performance and (iii) have come-up with few design proposals, which improves the device performance as well as reliability. These recent works are expected to change the way power MOSFETs were designed and used in integrated circuits. (We have published these works at forums like IEEE T-ED, IRPS, IEDM, SISPAD, ISPSD and EOSESD Symposium)

7. Record High Performance 600V e-mode GaN HEMT Technology

For the first time, a high- κ ternary gate oxide has been demonstrated as a potential candidate for achieving e-mode operation in AlGaN/GaN HEMTs. The ternary oxide was found to be similar to p-GaN gate for achieving e-mode HEMT operation. However, it allowed better channel control as a thin ternary oxide in conjunction with partial recess was capable to achieve a threshold voltage of 0.5V. Using the developed gate oxide, record high performance 600V class of e-mode device has been demonstrated with ON current ~400mA/mm, subthreshold slope of 73mV/dec, Ron = 9 Ω-mm, interface trap density < 1010 mm-2eV-1 and gate leakage below 200nA/mm at the OFF state breakdown. Based on experimental finding, a hybrid gate stack which combines pGaN technology with the developed dielectric for e-mode operation, has been proposed.

8. Deeper Insights in GaN HEMT Reliability Issues

Through 5 papers in IEEE IRPS (2016 – 2019) and 1 in IEDM (2018) we have revealed deeper insights and have highlighted fundamental issues related to reliability physics of GaN HEMTs. Besides, we have also developed deeper insights into the physics and role of C-doping of GaN buffers in AlGaN/GaN HEMTs. These insights have allowed us to engineer C-doping profile across GaN Epi-stack with improves the breakdown voltage as well as mitigates current collapse phenomena at the same time, without compromising on leakage current (The work on C-doping was published in IEEE T-ED).

9. High Performance 2D Material FET Technology

For the first time, atomic orbital overlap engineering for TMDs is proposed, which significantly improves the overall transistor performance without any hidden compromise. Understanding low temperature decomposition of H2S on TMD surface and quantum chemistry between transition metals, chalcogenides & contact metals have enabled the proposed atomic orbital overlap engineering to improve channel as well as contact performance and passivate/cure dangling bonds present in defected regions. These collectively have improved MoS2, WS2, MoSe2 and WSe2 FET’s characteristics by significant margins. Record high ON current for WS2 FET (240 mA/mm), at room temperature is demonstrated. Moreover, an overall record high performance improvement is achieved for MoS2, WS2, MoSe2 and WSe2 The proposed approach has been validated statistically across large set of devices. Besides, a novel way to get p-channel operation in WSe2 devices have been demonstrated.

Funding and Sponsors

A. Sanctioned / Approved

So. No.

Project Title

Agency

Value in Rs. (Lacs)

Duration

PI/Co-PI/Investigator

1

Institute Seed Grant for the Establishment of Advance Nanoelectronics Device & Circuit Research Laboratory

IISc

34

Oct 2013 – Sep 2014

PI

2

Demonstration of Graphene based RF Transistors

DRDO (SSPL)

10

June 2014 – Oct. 2014

PI

3

Exploration of Carrier Transport and Contact Resistance Behaviours in Carbon Nanotube and Graphene Devices Using Nanosecond Time Scale Charge Bust

DST (SERB)

51

July 2014 – June 2017

PI

4

Investigation on GaN devices for power electronic switching applications and design and development of a high frequency GaN convertors topology

NaMPET Phase-II

191

Oct. 2014 – March 2017

Co-PI

5

Advance Nanoscale Characterization Facility

IISc

110

Jan 2015 – Sep 2015

PI

6

ESD Reliability of sub-14nm node technologies

Intel, Germany

100

Dec 2015 – Nov. 2018

PI

7

12th Plan Grant to Develop Laboratory Space

IISc

5

Sep 2016 – March 2017

PI

8

Technology Development for 600V Normally – OFF Gallium Nitride Transistor for Reliable Power Electronic Systems

DST (TSDP)

1028

May 2016 – April 2019

PI

9

Graphene Based THz Transistor Technology

DRDO (ERIPR)

470

Dec 2016 – Nov. 2010

PI

10

High Voltage & ESD Device Development & Enablement in SCL’s 180nm CMOS Technology

IMPRINT

300

Jan 2017 – June 2019

PI

11

Detailed Project Report on GaN Foundry

DeitY

60

March 2016 – Sep. 2016

Co-PI

12

Power-scalability of Advance Semiconductor Devices from ESD time domain to DC

Texas Instruments (USA)

140

Oct 2017 – Sep 2010

PI

13

2D Material Based Flexible Electronics Technology: Towards High Performance Ultra Light Weight & Flexible Electronics

NNeTRA program of MeitY
(Under CEN-III)

7500

April 2018 – March 2022

Co-PI
(Investigator of sub-project)

14.

Exploratory Science Project under IOE

IISc/MHRD

200

August 2019

PI

15.

Reactor neutrons’ influence on the graphene electrophysical properties and implications for metal-graphene ohmic contact

DST-UKR Joint Call

14

April 2019 – March 2022

PI

16.

Development of Microelectronics Lab

IISc (MHRD)

150

March 2018 – Sep. 2018

PI

17.

Graphene Based Heat Spreader Technology

IMPRINT-II

140

August 2019 – July 2022

PI

Total Sanctioned Funding Till 2018

3300

Facility

Research Facility in MSDLab

This is a ~18 Crore worth facility. The unique capabilities of this facility are being extensively utilized, not just by PhD students in MSDLab, but also by staff and students from several other departments. In general, this facility has helped develop several technologies such as graphene and 2D materials technology, high power Gallium Nitride technology, organic electronics and Si based power technology. The users can independently handle the tool post a systematic training.

1. Manual Probe Station

Lab has 2 manual probe stations. The tool allows holding and probing samples of 1cm size to 8-inch wafers. The probe station houses a high-end microscope with magnification up-to 1000, which allows probing nano-meter sized devices for DC and RF tests at temperatures between 300K to 500K. Besides, its capable of measuring ultra-low currents, as well as very high currents and voltages. The vibration free table with pneumatic isolation using a low noise air compressor allows high precision probing of the devices.

2. Semi-automatic Probe Station

It enables automatic DC and RF device characterization (up to 110 GHz), wafer-level reliability, e-test, modelling, or yield analysis. It is equipped with probe station control software to automate the measure 1000s of devices with a single click.

3. Range of Wafer Level Electrical Characterization Equipment

The facility has the following electrical characterization tools.

Equipment Type

Make

Model

Specification

SMU (4 Nos)

Keithley 2400

Keithley 2400

General purpose SMU (100V, 1A)

SMU (2 Nos)

Dual Channel SMU

Keithley 2635B

Single Channel SMU capable of 1A DC (10A Pulse), 200V.

SMU

Dual Channel SMU

Keithley 2636B

Dual Channel SMU capable of 1A DC (10A Pulse), 200V

SMU

Dual Channel SMU

Keysight

Dual Channel SMU capable of 1A DC, 200V

HC SMU (2 Nos)

High Current SMU

Keithley 2651A

High Current SMU (Upto 50A in pulsed mode, 20A in DC mode)

HV SMU (7 Nos)

High Voltage SMU

Keithley 2657A

High Voltage SMU (Upto 3kV)

CV Meter

CVU

Keithley PCT-CVU

High voltage capacitance measurements

Switching Matrix

Switching Matrix

Keithley 707B

Six-slot semiconductor switch mainframe (8 input and 36 output ports)

High Power interface panel

Panel

Keithley 8020

Interface between the Parametric Curve Tracer (PCT), SMUs, probe station and test fixtures for wafer level high power measurements.

PNA -X Network Analyzer

VNA

Keysight N5247

67 GHz PNA- X for Semiconductor Characterization

Parametric Curve Tracer (2 Nos)

4200

4200A-SCS

Parametric curve tracer with automation capability and switching matric for semiconductor device characterization. It consists of 6 medium power SMU, 1 CVU and 2 pulse measurement units.

FFT Spectrum Analyzer

SR760

SR760

Single-channel 100 kHz FFT spectrum analyzer

Digital Phosphor Oscilloscope

DPO

DPO 70404C

4 GHz digital oscilloscope

High speed pulse generator

HSPG

AVR-E3-B-W3

100 V, 1 ns to 5000 ns pulse generator

Arbitrary Function Generator (3 Nos)

AFG

AFG1022

µHz to MHz, mV to 10 V, dual channel function generator

4 Channel Digital Storage Oscilloscope (2 Nos)

DSO

TBS1154

150 MHz, 4 channel oscilloscope

Lock-in Amplifier

MFLI

MFLI

500 kHz Lock-In Amplifier

4. Transmission Line Pulsing

Transmission line pulse setup is used to generate electrical pulses at a very high frequency with high amplitudes. At these frequencies, wavelength of electrical signal reaches the length scales of the testing setup and a proper pulse shaping is difficult. Due to these issues, a conventional SMU cannot be used for this purpose and a specialized strategy is needed. The TLP pulse generator works on the principle of transmission line pulsing technique. The TLP generator can generate pulses in pulse width range of 1ns-1.5 us with a maximum voltage level of 2 kV.

5. Micro Raman, EL/PL Setup with UV and Visible Lasers

Raman spectroscopy works on the principle of inelastic scattering of light by a material. As the light is applied on a material, the following interactions take place: Rayleigh scattering, Stokes scattering and Anti-stokes scattering.  Raman setup works on the principle of anti-stokes scattering and is used to study chemical and vibrational properties of a material. A laser source with a pre-determined wavelength and power density is used and a charge couple detector is used to capture photons emitted from the material upon interaction with light. The setup has the following two light sources: (1) DPSS, green-colour, 532 nm and (2) UV light, 325 nm. The setup also comprises of electrical part used to study material change with stress application. A cryogenic pump, with an ability of cool down as low as 4K, is integrated with the Raman setup to study device interactions at extremely low temperatures. This study is used to study ambient interactions, photoluminescence, electroluminescence, impact of electrical stress on chemical properties and low temperature vibrational properties of a material.

7. Custom Setup for 2D Material Based Stamping and Device Fabrication inside Glovebox

This custom developed tool provides an inert environment for fabrication of devices using materials sensitive to oxygen and moisture (less than 1ppm of Oxygen and moisture). This enables development of heterostructures using dry transfer setup called stamping stage having high magnification (2000x) microscope and range of nano-manipulators, provides an efficient way to explore fundamental properties and application specific behaviour of various potential materials for electronic applications. The setup also consists of thermal evaporator for metal deposition and wet-bench. Such an assembly of stamping stage and thermal evaporator inside inert atmosphere enables an ultra-clean process for device fabrication.

8. 3K Ultra Low Vibration Close-Loop Cryocooler for Optical and Electrical (DC & RF) Measurements

This tool allows loading devices under ultra-low temperature (3K) condition and enables optical as well as electrical excitations / measurements.

9. L-N2 Semi-automatic Probe Station

This is a L-N2 based semi-automatic probe station. The tool enables DC and RF device characterization, wafer-level reliability, e-test, modelling, or yield analysis for a temperature ranging from 77K to 550K. It is equipped with a probe station control software to automate measurements for 1000s of devices.

10. Deep Level Transient Spectroscopy

This tool allows probing deep level defect / trap states in materials.

11. Thermo Reflectance Spectroscopy

This tool allows probing temperature across a nanoscale device with sub-400nm special resolution and sub-ns time resolution.

12. Wafer Level Semiconductor Device Reliability Characterization Suit

This tool allows to study high field reliability behaviour of semiconductor devices such as HCI, TDDB, NBTI, PBTI and other similar issues in emerging devices.

13. High End Computational Cluster

With over 250 Cores and 6TB RAM, this is among the most powerful cluster being used for TCAD simulations and Atomistic computations.

14. Parametric Curve Tracer with sub-50ns pulse I-V measurement capability

The lab has two such systems from Keithley (Keithley 4200 SCS), which consists of 6 medium power SMUs (each), capacitance-voltage measurement unit and two sets of pulse measurement units (PMU). It allows measurement from fA to A. It can also measure pulse I-V characteristics with 50ns pulse width.

15. 1/f Noise Measurement Setup

This enables 1/f Noise measurements in range of devices.

16. 3-Omega setup for thermal conductivity measurements

 

Research Group

  • 15 PhD students
  • 2 # M-Techstudents, 4 # JRF/SRF (2 Nano, 2 Power/HV) and 5 # PDFs

Postdoctoral Fellow

  1. Nikhil K S (PhD IIT Madras)
  2. Vipin Joshi (PhD IIT Jodhpur)
  3. Asha Yadav (PHD IIT Guwahati)
  4. Jhnanesh Somayaji (PhD NIT Surathkal)
  5. Ajay (PhD Delhi University)

PhD Students

  1. Anand Rai
  2. Utpreksh Patbhaje
  3. Rupali Verma
  4. Om Kesharwani
  5. Rajarshi Roy Chaudhuri
  6. Monish Murali
  7. Harsha B
  8. Jeevesh Kumar
  9. Sayak Dutta Gupta
  10. Kranthi N. K. – Graduating in 2020
  11. Ankit Soni – Graduating in 2020
  12. Hemanjaneyulu Kuruva – Graduating in 2020
  13. Ansh – Graduating in 2020
  14. Rajat Sinha – Graduating in 2020
  15. Bhawani Shankar – Graduating in Oct. 2019
  16. Adil Meersha – Graduating in Oct. 2019
  17. Abhishek Mishra – Graduated in August 2019
  18. Milova Paul – Graduating in Oct. 2019
  19. Sampath B – Graduating in Dec. 2019

JRF/SRF

  1. Gaurav Sheoran
  2. Sirsha Guha
  3. Neeraja N.
  4. Anant Kumar Singh
  5. Siddharth Sinha

Teaching and Workshops

#
Course No.

Course title

Nature

Term

1

E3 282 Basics of Semiconductor Devices and Technology

Core

August

2

E3 200 Microelectronics Lab

Core

August

3

E3 275 Physics and Design of Transistors

Soft Core

Jan

4

E3 274 Design of Power Semiconductor Devices

Soft Core

Jan

5

E3 271 Reliability of Nanoscale Circuits and Systems

Soft Core

Jan

Conferences and Workshops Hosted :

  1. IEEE EDS/SSCS Bangalore Chapter Chair (Since Dec 2015). In this role I have hosted more than 25 international experts from around the world (see list enclosed).
  2. 3rd India ESD Workshop (Feb 2019): This was the third edition of India ESD workshop, which ran for 2 days. This time it was driven by VLSI industry in Bangalore with a total (paid) participation above 200. The workshop hosted 4 keynote talks by renowned international ESD experts, 2 tutorial talks, 14 invited talks and 15 poster presentations.
  3. Organized 3rd IEEE CONECCT (March 2013), which was attended by over 250 participants with around 100 Oral and poster papers. The conference ran for 2 days with 4 keynote talks and 4 parallel technical sessions.
  4. Organized 4th IEEE ICEE (Dec 2018), which was attended by over 650 participants. The conference ran for 4 days with over 20 tutorial talks and 8 keynote talks. Besides, ICEE had 160 invited talks, 102 Oral papers and 125 poster papers, divided in 10 parallel technical sessions.
  5. 2nd India ESD Workshop: This was the second edition of India ESD workshop, as part of India ESD forum formed in year 2016. This time it was much more professionally organized with over 80 registrations. The event was covered by ESD Association’s (USA) newsletter, IEEE EDS newsletters, as well as several online media houses, which are published internationally.
  6. Offered a 3 day ESD course / workshop to X-Fab engineers in Kuching, Malaysia. This was fully funded by X-Fab and was registered by over 25 X-Fab engineers.
  7. 1st India ESD Workshop: 1 day workshop on on-chip ESD design, hosted in IISc. Single-handedly formed a forum or nationwide special interest group called “India ESD Forum”, which today has over 60 industry members. This workshop was attended by over 30 industry senior engineers / managers. The event was covered by ESD Association’s (USA) newsletter, which is published internationally.
  8. ESD Design Essentials: 2 day workshop hosted at Hotel Oberoi, Bangalore. This was technically and financially sponsored by ESDA, USA.

Recognitions

Professional Recognitions, Awards, and Fellowships:

  1. National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018
  2. Indian National Academy of Science (INSA) Young Scientist Award, 2018
  3. Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation)
  4. Indian National Academy of Engineering (INAE) Young Engineer Award, 2017
  5. 2015 IEEE EDS Early Career Award, one of the highest honors given by IEEE Electron Device Society (EDS).
  6. INAE Young Associate (since 2017)
  7. Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023
  8. IEEE Senior Member (since August 2016)
  9. Department of Electronics & Information Technology (DeitY), Govt. of India, Young Faculty Fellowshipfor the duration of 2016 – 2020.
  10. Outstanding Paper Award, 38th EOSESD Symposium, 2017
  11. Outstanding Paper Award, VLSI Design Conference, Jan. 2017
  12. Editor for Electronic Devices and Components of IETE Journal of Research (2014 – 2016)
  13. Editor for Elsevier Microelectronic Reliability (2018 – 2020)
  14. TR35, 2010, Young Innovator Award. Technology Review’s TR35 list by Massachusetts Institute of Technology recognizes the outstanding innovators under the age of 35 each year. Received on March 8, 2010
  15. Award for Excellence in Thesis Work, IIT Bombay-2010, received on 6th August, at the 48th convocation of IIT Bombay.
  16. IIT Bombay – Industrial Impact Award, for pursuing research work that caused maximum industry impact. Received on September 6, 2010 by Dr. N. Mukunda, who is a prominent Indian scientist.
  17. Best Research paper Award, Intel Asia Academic Forum 2008, Oct 2008, Taipei, Taiwan
  18. Infineon Fellowship, Duration: November 2008- July 2010
  19. Technical Program Committee (TPC) IEDM and IRPS are the two most prestigious conferences
    1. IEEE International Electron Device Meeting (IEDM), USA, 2018 – 2019
    2. IEEE International Reliability Physics Symposium (IRPS), USA 2017, 2018 & 2019
    3. EOSESD Symposium, USA: 2012 – 2018 (Sub-committee chair in 2014 & 2017)
    4. IEEE EDTM, Singapore 2019
    5. IEEE ESSDERC, Europe: 2014 – 2016
    6. IEEE ESREF, Europe, 2019
    7. IEEE ICEE – 2018 (TPC Chair)
    8. IEEE CONECCT – 2018 (Gen. co-Chair and TPC Chair)
    9. IEEE VLSI Design 2014 & 2015 (Vice-chair, “Device and Process Technology” session)

Publicity / Popular Recognition

With IISc Affiliation:

Rajya Sabha TV: https://www.youtube.com/watch?v=ASJ2H-NV7hw
Research Matters: https://researchmatters.in/news/iisc-develops-india%E2%80%99s-first-e-mode-gallium-nitride-power-transistor
Times of India: https://timesofindia.indiatimes.com/home/science/iisc-faculty-change-game-with-indias-first-e-mode-gallium-nitrade-power-transistor/articleshow/69661844.cms
Electronic for You: https://academia.electronicsforu.com/iisc-researchers-develop-indias-first-e-mode-gallium-nitride-power-transistor
Northbound: http://www.northbound.co.in/engineering-phd/
Research Matters: https://researchmatters.in/news/iisc-research-pushes-reliability-and-operating-limits-ultra-dense-finfet-system-chips
EE Herald: http://www.eeherald.com/section/news/owns20171225001-india-ee-edu.html
Research Matters: https://researchmatters.in/article/inae-announces-young-engineer-awards-2017
India DST: https://indiadst.wordpress.com/2017/01/20/iisc-researchers-develop-new-graphene-based-transistor-technology/
Scientifist: http://scientifist.com/iisc-researchers-graphene-electronics/
Indian Express: http://indianexpress.com/article/technology/science/breaking-the-graphene-barrier-4465396/
Bangalore Mirror: http://bangaloremirror.indiatimes.com/bangalore/others/iisc-can-make-your-wifi-1000-times-faster/articleshow/56091767.cms
IISc Press: https://researchmatters.in/article/iisc-scientists-new-discovery-yields-giant-leap-graphene-transistor-performance
The Better India: http://www.thebetterindia.com/79060/iisc-working-making-wifi-1000-times-faster/
UC News: http://www.ucnews.in/news/702-513932134192309/a-team-of-researchers-from-iisc-bangalore-could-make-our-wifi-1000-times-faster.html
Yahoo: https://in.news.yahoo.com/team-researchers-iisc-bangalore-could-095934372.html
Indian 364: http://www.indian364.com/technology/26961/Breaking-the-graphene-barrier
Research Matters: https://researchmatters.in/article/iisc-scientists-new-discovery-yields-giant-leap-graphene-transistor-performance
Rajya Sabha TV: https://youtu.be/k9u2Ji9Vlbk
Bangalore Mirror: http://www.bangaloremirror.com/bangalore/others/New-transistor-design-is-a-breakthrough/articleshow/49897633.cms
Indian Express: http://indianexpress.com/article/technology/technology-others/from-the-lab-a-new-device-for-more-efficient-phones-computers/
IISc Press: http://iisc.researchmedia.center/article/iisc-researcher%E2%80%99s-new-transistor-design-%E2%80%93-breakthrough-chip-technology
Indian Express: http://www.newindianexpress.com/cities/bengaluru/IISc-Prof-Wins-Major-Global-Award/2015/10/29/article3102225.ece
Deccan Herald: http://www.deccanherald.com/content/515146/bengaluru-scientist-wins-coveted-ieee.html
Hindu: http://www.thehindu.com/news/cities/bangalore/honour-for-iisc-professor/article7816056.ece
Global Indians: http://www.globalindian.indiaincorporated.com/iisc-prof-wins-major-global-award/
IEEE: http://eds.ieee.org/early-career-award.html
IISc Press:: http://iisc.researchmedia.center/article/iisc-professor-wins-major-international-award
Deccan Herald: http://www.deccanherald.com/content/509822/iisc-faculty-devises-technology-shrink.html
News Central: http://newscentral.exsees.com/item/8563b69c9b5b9519487c36e18dcedb90-f39db1effc9ea34e1d52a76b94b3ea02
Gas & Electricity: http://gaselectricity.in/iisc-faculty-devises-technology-to-shrink-power-electronic-systems
Daily Hunt: http://m.dailyhunt.in/news/india/english/deccan-herald-epaper-deccan/iisc-faculty-devises-technology-to-shrink-power-electronic-systems-newsid-45850179
Nyooz: https://www.nyoooz.com/news/bengaluru/245362/iisc-prof-wins-major-global-award/
GK Today: https://www.gktoday.in/quiz-questions/who-became-the-first-indian-to-bag-ieee-electron-devices-society-early-career-award/

Before joining IISc:

Technology Review: http://www2.technologyreview.com/tr35/profile.aspx?TRID=860
DNA: http://www.dnaindia.com/india/report-iit-b-makes-it-to-mit-s-top-innovators-list-1361475
Deccan Herald: http://www.deccanherald.com/content/58465/beyond-classroom.html
Indian Express: http://www.indianexpress.com/news/towards-smaller-better-gadgets/587650/0
NDTV: http://www.ndtv.com/news/sci-tech/iit_infineon_achieve_breakthrough_for_system-on-chip.php
EE Herald: http://www.eeherald.com/section/news/nw10000592.html
EE Times: http://www.eetimes.com/author.asp?section_id=36&doc_id=1284049
EE Times: http://www.eetimes.com/electronics-news/4083184/Infineon-Indian-researchers-claim-ESD-advance
Rediff: http://business.rediff.com/report/2009/apr/22/iit-achieves-breakthrough.htm

Invited Talks

Invited Talks (Other than peer reviewed presentations)

  1. ESD Device Physics of Advance and Beyond CMOS Devices
    • Intel Corp., Munich, Germany (July 27th 2018)
    • Infineon Technology, Munich, Germany (July 28th 2018)
    • Intel Corp., Portland, USA (Sep 19th 2018)
    • NXP, Nijmegen, Netherlands (June 29th, 2018)
  2. The Future of World Electronics and the Possible Role India Can Play
    • Workshop on Microelectronics and Information Security, SSPL, Ministry of Defense, Oct. 2018
    • 41st Annual event of KSCST (August 12th 2018)
    • Innovation Bazar, Western Digital (July 6th 2018)
    • IEEE Talk, Madras Chapter (Dec 26th 2017)
    • SSPL, DRDO (Oct. 2017)
    • IEEE Region – 10 Golden Jubilee Event, August 5th, 2017 (Key Note Talk)
    • 51st Computer Society of India Conference (Memorial Talk, Jan. 24th 2016)
    • IEEE Golden Jubilee Congress (August 2016)
    • IISc EECS Symposium (Feb 2016)
  3. Gallium Nitride Electronics: Design and Reliability
    • University of Padova, Padova, Italy (July 3rd 2018)
    • Infineon Technology, Villach, Austria (July 2nd 2018)
    • Online webinar organized by ESD Association USA, telecasted globally on 29th 2017.
    • IWPSD, Dec. 2017
    • ITC-India, July 2017
    • ICYRAM-2016, Dec. 14th 2016
    • Texas Instruments, Dallas, April 8th 2017
    • Semiconductor Complex Limited (SCL), Department of Space, May 2017
    • IEEE Conference, July 11th, 2017
    • International conference on Emerging Electronics, Dec. 5th 2014
  4. Record High Performance CVD Graphene Transistor
  • University of Budweiser, Munich, Germany, July 4th 2018
  • ISIF, Dec, 2017
  • IEEE International Conference on Emerging Electronics, Dec. 27th 2016
  • IIT Delhi, Jan 9th 2017
  • IIT Kanpur, Jan 10th 2017
  1. Performance & Reliability Co-Design Approach for High Voltage LDMOS Devices
    • NXP, Nijmegen, Netherlands (June 29th, 2018)
    • Semiconductor Complex Limited (SCL), Department of Space, July 2nd 2015
    • ANURAG, DRDO, Feb 2017
    • LRDE, DRDO, Feb 2017
  2. “On Chip ESD Design: Why EDA Based Approach is Becoming Important?”, Key Note talk at Cadence India Design Center, Dec 11th 2015
  3. On-Chip ESD Devices and Circuits: Essentials and Research Opportunities
  • 2nd India ESD Workshop, March 17th, 2017
  • 1st India ESD Workshop, Feb 26th, 2016
  • IIT Gandhinagar, Dec. 31st 2015
  • Semiconductor Complex Limited (SCL), Department of Space, July 1st 2015
  • EE Department, IIT Madras, July 2014
  • Texas Instruments Bangalore, India, April 2014
  • CRL Bangalore, Feb. 2014
  • Fifth Electrical Sciences Symposium, IISc Bangalore, Feb. 2014
  1. “ESD Design Essentials”, Bangalore, 8th and 9th 2015
    • ESD Device Physics
    • On-Chip ESD (Circuit) Design
    • CDM Phenomena and Protection Design
    • Latch-up
  2. ESD Robust LDMOS Design Essentials” Online webinar organized by ESD Association USA, telecasted globally in Nov. 2014.
  3. IC and System Design for Electrostatic Discharge Protection”, IEEE INDICON, Dec. 2013
  4. Drain extended MOS device design and reliability challenges” IWPSD Dec. 2013
  5. A Review on the ESD Robustness of Drain Extended MOS Devices” International ESD workshop, May 20, 2013, Warrenton, VA, USA
  6. 3D TCAD Based approach for ESD failure analysis“, Infineon Technologies, AG, Munich (Germany), June 2010.
  7. Reliability aware I/O design for sub 45nm node CMOS technology” IWPSD-2009, 18th Dec, 2009.
  8. Benchmarking the device performance at sub 22 nm node technologies using an SoC framework“, IWSG-2009, 3rd Dec 2009.
  9. 3D filament behavior of various HV DeMOS devices under ESD condition” University of California (SB), USA, 4th Sep, 2009.
  10. Filament behavior of various DeMOS devices“, Technical University of Vienna, Austria, 8th Oct 2008.
  11. ESD optimization of DeMOS devices“, Infineon Technologies, AG, Munich (Germany), 6th Oct 2008.
  12. Mixed signal and hot carrier performance of various DeMOS devices” Infineon Technologies, AG, Munich (Germany), 3rd May 2008.

Patents

Granted/Issued (United States Patent Office):

  1. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei,” Semiconductor devices with trench isolations”, United States Patent (2012) 8,097,930
  2. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “Operational Amplifier Having Improved Slew Rate ” United States Patent (2012) 8,089,314
  3. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Nonvolatile floating gate analog memory cell”, United States Patent (2013) 8,436,413
  4. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (2013) 8,354,710
  5. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, Ramgopal Rao, Christian Russ, “Device and method for coupling first and second device portions”, United States Patent (2013) 8,455,947
  6. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (2013) 8,536,648
  7. Mayank Shrivastava and Harald Gossner, “Drain extended MOS device for Bulk FinFET technology”, United States Patent (2014) 8,629,420
  8. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Semiconductor devices and methods for manufacturing a semiconductor device”, United States Patent (2014) 8,643,090
  9. Mayank Shrivastava, Christian Russ, Harald Gossner, “Low voltage ESD clamping using high voltage devices”, United States Patent (2014) 8,654,491
  10. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (2014) 8,664,720
  11. Mayank Shrivastava, Christian Russ, Harald Gossner, “Selective current pumping to enhance low-voltage ESD clamping using high voltage devices”, United States Patent (2014) 8,681,461
  12. Mayank Shrivastava and Harald Gossner, “Silicon controlled rectifier (SCR) device for bulk FinFET technology”, United States Patent (2015) 8,785,968
  13. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable Fin-SCR for Robust ESD Protection”, United States Patent (2015) 8,963,201
  14. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-Effect Device and Manufacturing Method Thereof”, United States Patent (2015) 9,035,375
  15. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain Extended Field Effect Transistors and Methods of Formation Thereof”, United States Patent (2015) 9,087,892
  16. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements for electrostatic (ESD) protection”, United States Patent (2016) 9,356,013
  17. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, Ramgopal Rao, “Methods for manufacturing a semiconductor device”, United States Patent (2016) 9,368,573
  18. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (2016) 9,401,352
  19. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (2016) 9,455,275
  1. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable FIN-SCR for Robust ESD Protection”, United States Patent (2017) 9,608,098.
  2. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements including dummy gates for electrostatic discharge protection”, United States Patent (2017) 9,595,516.
  3. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (2017) 9,647,069.
  4. Mayank Shrivastava and Christian Russ, “FinFET and Fin-BJT SCR as ESD clamp with Built-In trigger circuit and Current Ballasting mechanism including Checker-Board Layout Technique for Uniform SCR Turn-On”, United States Patent (2015) 20150008476.
  5. Christian Russ, Mayank Shrivastava and Markus Schwiegershausen, “Transient-Triggered SCR for FinFET Technology (FF-TTSCR) for ESD Protection of RF IO”, United States Patent pending (Filed August 2015).
  6. Milova Paul, Mayank Shrivastava, Sampath Kumar, Christian Russ and Harald Gossner, “Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device”, US Patent Pending, Application No: 15/883,306, Filed on: 30-Jan-18 (Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017)
  7. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Non-planar Electrostatic Discharge (ESD) Protection Devices With Nano Heat Sinks”, US Patent Pending, Application No: 15/883,749, Filed on: 30-Jan-18 (Indian Patent, Application No 201741003773, Filed on 1st Feb. 2017)
  8. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Low Trigger and Holding Voltage Silicon Controlled Rectifier (SCR) For Non-Planar Technologies”, US Patent No (2019): 10,211,200 (Indian Patent, Application No 201741003772, Filed on 1st Feb. 2017)
  9. Mayank Shrivastava, Milova Paul and Harald Gossner, “FinFET SCR With SCR Implant Under Anode And Cathode Junctions”, US Patent Pending, Application No: 15/899,102, Filed on: 19-Feb-18 (Indian Patent, Application No 201741006746, Filed on 25th Feb. 2017)
  10. Mayank Shrivastava, Milova Paul and Harald Gossner, “Electrostatic Discharge (ESD) Protection Devices For ESD Robustness And Latch-Up Immunity”, US Patent Pending, Application No: 15/899,117, Filed on: 19-Feb-18 (Indian Patent, Application No 201741006745, Filed on 25th Feb. 2017)
  11. Mayank Shrivastava, “Drain extended Tunnel FET”, US Patent Pending, Application No: 15/439,951, Filed on: 23-Feb-17 (Indian Patent Application No: 201641006497, Filed on Feb 26th 2016.)
  12. Mayank Shrivastava, Recess Gate Superjunction High-electron-mobility transistor (HEMT)”, US Patent Pending, Application No: 20190081164 A1 (Indian Patent Application 201741024695, July 2017.)
  13. Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni and Srinivasan Raghavan, “e-Mode Field Effect High Electron Mobility (HEMT) Transistor”, US Patent Pending, Application No: 20190067440 A1 (Indian Patent Application 201741030570, August 2017)
  14. Mayank Shrivastava and Vipin Joshi, “Doping and Trap Profile Engineering In Gan Buffer To Maximize Algan/GaN Hemt Epi Stack Breakdown Voltage”, US Patent Pending (Indian Patent Application 201841020899, Filled on June 5th 2019)

Patent Pending:

  1. Rohit Soman, Ankit Soni, Mayank Shrivastava, S. Raghavan and Navakanta Bhat “GaN HEMT Device with high Breakdown Voltage”, Indian Patent Application, May 2017
  2. Ansh, Hemanjaneyulu Kuruva and Mayank Shrivastava, “Methods Of Manufacturing 2-Dimentional Semiconductor Transistors”, Indian Patent Application 201741033081, September, 2017
  3. N. S. Kranthi, K. Hemanjaneyulu, and Mayank Shrivastava, “ESD Robust Tunnel FET Device”, Indian Patent Application 201741025123, July 2017
  4. Mayank Shrivastava and Kuruva Hemanjaneyulu “Fin enabled area scaled tunnel field Effect transistor”, Patent Application No: 2625/CHE/2015, Filed on May 26th 2015.
  5. Mayank Shrivastava, “Miniaturized, High Power Density Power Electronic System on a Chip”, Patent Application No: 1355/CHE/2015, Filed on March 19th 2015.
  6. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Independently Driven Double Gate (IDDG) Nonvolatile floating gate analog memory cell”, Indian Patent pending, 2008, Patent Application No 2217/MUM/2008, Filed on 15th October 2008.
  7. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, ” A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, Patent Application No 542/MUM/2010, Filed on 2nd March 2010.

List of Publications

Over 100 publications in IEEE Journals or Conferences of high repute. Except journal paper # 33 & 38, all other publications have resulted from work done in India. Total 23 publications in the IEEE International Electron Devices Meeting (IEDM) & the IEEE International Reliability Physics Symposium (IRPS), which are the two most prestigious conferences for Electron Devices (All of these have resulted from work done in India).

Books, Book chapters and Technical Briefs

  1. Chapter titled “Towards Drain extended FinFETs for SoC applications” in book “Toward Quantum FinFET”, edited by Weihua Han and Zhiming M. Wang, Springer, Dec. 2013, ISBN 978-3-319-02021-1.
  2. Mayank Shrivastava and V. Ramgopal Rao, “Tunnel Field Effect Transistors”, Present, Past and Future, Technical Brief appeared in the IEEE EDS Newsletters, July 2016 (Cover page article).

 Peer Reviewed International Journals

  1. Bhawani Shankar and Mayank Shrivastava, “Safe Operating Area of Polarization Super Junction GaN HEMTs & Diodes”, IEEE Transactions on Electron Devices, Volume: 66, Issue:9, Page(s): 3756-3763, September 2019, DOI: 10.1109/TED.2019.2926781
  2. Ankit Soni, Swati Shikha and Mayank Shrivastava, “On the Role of Interface States in AlGaN/GaN Schottky Recessed Diodes: Physical Insights, Performance Tradeoff, and Engineering Guidelines”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019. DOI: 10.1109/TED.2019.2912783
  3. Hemanjaneyulu Kuruva, Jeevesh Kumar and Mayank Shrivastava, “MoS2 Doping using Potassium Iodide for Reliable Contacts and Efficient FET Operation”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 7, July 2019, Page(s): 3224 – 3228. DOI: 10.1109/TED.2019.2916716
  4. Sayak Dutta Gupta, Ankit Soni, Rudrarup Sengupta, Heena Khand, Bhawani Shankar, Nagboopathy Mohan, Srinivasan Raghavan, Navakanta Bhat, and Mayank Shrivastava, “Positive Threshold Voltage Shift in AlGaN/GaN HEMTs & E-mode Operation by AlxTi1-xO based Gate Stack Engineering”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019, Page(s): 2544 – 2550. DOI: 10.1109/TED.2019.2908960
  5. Rajat Sinha, Prasenjit Bhattacharya, Tim Iben, Sanjeev Sambandan and Mayank Shrivastava, “ESD Reliability Study of a-Si:H Thin film Transistor Technology: Physical Insights and Technological Implications”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 6, June 2019. DOI: 10.1109/TED.2019.2913040
  6. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan and Mayank Shrivastava, “ESD Behavior of AlGaN/GaN Schottky Diodes”, IEEE Transactions on Device and Materials Reliability, Volume: 19, Issue: 2, June 2019, Page(s): 437 – 444. DOI: 10.1109/TDMR.2019.2916846 (Invited Paper)
  7. Bhawani Shankar, Ankit Soni, Hareesh Chandrasekar, Srinivasan Raghavan and Mayank Shrivastava, “First Observations on the Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Volume: 66, Issue: 8, Aug. 2019, Page(s): 3433 – 3440. DOI: 10.1109/TED.2019.2919491
  8. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior of AlGaN/GaN HEMTs”, IEEE Transactions on Device and Materials Reliability, Volume: 19, Issue: 2, June 2019, Page(s): 437 – 444. DOI: 10.1109/TDMR.2019.2916846
  9. Nagothu Karmel Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene Transistors: Physical Insights and Technology Limitations”, IEEE Transactions on Electron Devices, Vol, 66, Issue: 1 , Pages: 743 – 751, Jan. 2019. (DOI: 10.1109/TED.2018.2877693), (Year 2017 Impact Factor: 2.62)
  10. Vipin Joshi, Shree Prakash Tiwari, and Mayank Shrivastava, “Part-I: Physical insight into breakdown voltage improvement with Carbon doping in AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Vol., 66, Issue: 1 , Pages: 561 – 569, Jan. 2019. (DOI: 10.1109/TED.2018.2878770)  (Year 2017 Impact Factor: 2.62)
  11. Vipin Joshi, Shree Prakash Tiwari, and Mayank Shrivastava, ” Part II: Proposals to Independently Engineer Donor and Acceptor Trap Concentrations in GaN Buffer For Ultra High Breakdown AlGaN/GaN HEMTs”, IEEE Transactions on Electron Devices, Vol., 66, Issue: 1 , Pages: 570 – 577, Jan. 2019. (DOI: 10.1109/TED.2018.2878787) (Year 2017 Impact Factor: 2.62)
  12. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner, Mayank Shrivastava, “Challenges & Physical Insights into the Design of Fin Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection”, IEEE Transactions of Electron Devices, Vol, 65, Issue: 11, Pages: 4755 – 4763, Nov. 2018. (DOI: 10.1109/TED.2018.2869630) (Year 2017 Impact Factor: 2.62)
  13. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Devices Under ESD Condition Revisited “, IEEE Transactions on Electron Devices, Vol, 65 , Issue: 7, pp. 2981 – 2989, July 2018. (DOI: 10.1109/TED.2018.2835831) (Year 2017 Impact Factor: 2.62)
  14. Abhishek Mishra, Adil Meersha, Srinivasan Raghavan and Mayank Shrivastava, “Observing Non-equilibrium State of Transport through Graphene Channel at the Nano-Second Time Scale”, Applied Physics Letters, Vol. 111, Issue: 26, Pages: 263101-6, Dec. 2018. (DOI: 10.1063/1.5006258) (Year 2017 Impact Factor: 3.495, Five-Year Impact Factor: 3.386)
  15. B Sampath Kumar and Mayank Shrivastava, “Part I: On the Unification of Physics of Quasi-Saturation in LDMOS Devices”, IEEE Transactions on Electron Devices, Vol. 65, Issue: 1, Pages: 191-198, Jan. 2018. (DOI:10.1109/TED.2017.2777004 ) (Impact Factor: 2.62)
  16. B Sampath Kumar and Mayank Shrivastava, “Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi Saturation”, IEEE Transactions on Electron Devices, Vol. 65, Issue: 1, Pages: 199-206, Jan. 2018. (DOI:10.1109/TED.2017.2732504 ) (Impact Factor: 2.62)
  17. Abhishek Misra, Harald Gossner and Mayank Shrivastava, “ESD Behavior of MWCNT Interconnects – Part I: Observations and Insights”, IEEE Transactions on Device and Material Reliability, Vol. 17, Issue: 4, Pages: 600-607, Dec. 2017. (DOI:10.1109/TDMR.2017.2756924 ) (Invited Review Paper) (Impact Factor: 1.512)
  18. Abhishek Misra and Mayank Shrivastava, “ESD Behavior of MWCNT Interconnects – Part II: Unique Current Conduction Mechanism”, IEEE Transactions on Device and Material Reliability, Vol. 17, Issue: 4, Pages: 608-615, Dec. 2017. ( DOI:10.1109/TDMR.2017.2738701 ) (Invited Review Paper) (Impact Factor: 1.512)
  19. Jhnanesh Somayaji, B.Sampath Kumar, M. S. Bhat, Mayank Shrivastava, “Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices “, IEEE Transactions on Electron Devices, Vol, 64, Issue: 10 , Pages: 4175 – 4183, Oct. 2017.  (DOI: 10.1109/TED.2017.2733043 ) (Impact Factor: 2.62)
  20. Abhishek Mishra, Ravi Nandan, Srinivasan Raghavan and Mayank Shrivastava, ” Nano-second time resolved investigations on thermal implications of high-field transport through MWCNTs”, Applied Physics Letters, Vol. 110, Pages:  233111-6, May 2017. (https://doi.org/10.1063/1.4984282 )  (Impact Factor: 3.495, Five-Year Impact Factor: 3.386)
  1. Abhishek Mishra and Mayank Shrivastava, “Remote Joule Heating Assisted Carrier Transport in MWCNTs Probed at Nanosecond Time Scale”, Physical Chemistry Chemical Physics (PCCP) Journal of Royal Society of Chemistry, Vol. 18, Pages: 28932-28938, Jun 2016. (DOI:10.1039/C6CP04497B) (Impact Factor: 3.906)
  2. Mayank Shrivastava, “Drain Extended Tunnel FET – A Novel High Voltage Device for Beyond FinFET System on Chip & Automotive Applications”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 2, Pages: 481 – 487, Feb. 2017. (DOI:10.1109/TED.2016.2636920 ) (Impact Factor: 2.62)
  3. Vipin Joshi, Ankit Soni, Shree Prakash Tiwari and Mayank Shrivastava, “A Comprehensive Computational Modeling Approach for AlGaN/GaN HEMTs”, IEEE Transactions on Nanotechnology, Vol. 15, Issue: 6, Pages: 947 – 955, Nov. 2016. (DOI:10.1109/TNANO.2016.2615645 ) (Impact Factor: 2.857)
  1. Kranthi Nagothu and Mayank Shrivastava, “On the ESD Behavior of Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 64, Issue: 1, Pages: 28 – 36, Jan. 2017. (DOI:10.1109/TED.2016.2630079 ) (Impact Factor: 2.62)
  2. Kuruva Hemanjaneyulu and Mayank Shrivastava, “Fin Enabled Area Scaled Tunnel FET”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3184- 3191, Oct. 2015. (DOI:10.1109/TED.2015.2469678 ) (Impact Factor: 2.62)
  3. Mayur Ghatge and Mayank Shrivastava, “Physical Insights On the Ambiguous Metal Graphene Interface and Proposal for Improved Contact Resistance”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 12, Pages: 4139- 4147, Dec 2015. (DOI:10.1109/TED.2015.2481507 ) (Impact Factor: 2.62)
  4. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, Harald Gossner, and V. Ramgopal Rao, “On the Improved High-Frequency Linearity of Drain Extended MOS Devices”, IEEE Microwave and Wireless Components Letters, Vol. 26, Issue: 12, Pages: 999-1001, Dec. 2016. (DOI:10.1109/LMWC.2016.2623239 ) (Impact Factor: 2.169)
  5. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain Extended PMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 12, Pages: 4097- 4104, Dec 2015. (DOI:10.1109/TED.2015.2481899 ) (Impact Factor: 2.62)
  6. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, “Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device”, IEEE Transactions on Electron Devices, Vol. 62, Issue 12, Pages: 4105-4113, Dec 2015. (DOI:10.1109/TED.2015.2488683 ) (Impact Factor: 2.62)
  7. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part II: A Fully Integrated RF PA in 28nm CMOS with Device Design for Optimized Performance and ESD Robustness”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3176-3183, Oct. 2015. (DOI:10.1109/TED.2015.2470109 ) (Impact Factor: 2.62)
  8. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Part I: High Voltage MOS Device Design for Improved Static and RF Performance”, IEEE Transactions on Electron Devices, Vol. 62, Issue: 10, Pages: 3168- 3175, Oct. 2015. (DOI:10.1109/TED.2015.2470117 ) (Impact Factor: 2.62)
  9. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “On the Geometrically Dependent Quasi-Saturation and gm Reduction in Advanced DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 63, Issue: 4, Pages: 1621 1629, April 2016. (DOI:10.1109/TED.2016.2528282 ) (Impact Factor: 2.62)
  10. Mayank Shrivastava, Neha Kulshrestha and Harald Gossner, “ESD Investigations of Multiwalled Carbon Nanotubes”, IEEE Transactions on Device and Material Reliability, Vol. 14, Issue: 1, Pages: 555 – 563, March, 2014. (DOI:10.1109/TDMR.2013.2288362 ) (Impact Factor: 1.512)
  11. Peeyush Swain, Mayank Shrivastava, Harald Gossner, M. S. Baghini and V. Ramgopal Rao, “Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 11, Pages: 3827-3834, November, 2013. (DOI:10.1109/TED.2013.2283421 ) (Impact Factor: 2.62)
  12. Anukool Rajoriya, Mayank Shrivastava, Harald Gossner, Thomas Schulz and V. Ramgopal Rao “Sub 0.5V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET Devices”, IEEE Transactions on Electron Devices, Vol. 60, Issue: 8, Pages: 2626-2633, August, 2013. (DOI:10.1109/TED.2013.2270566 ) (Impact Factor: 2.62)
  13. Mayank Shrivastava and Harald Gossner, “A Review on the ESD Reliability of Drain Extended MOS Devices”, IEEE Transactions on Device and Material Reliability, Vol. 12, Issue: 4, Pages: 615-625, December, 2012. (DOI:10.1109/TDMR.2012.2220358 ) (Invited Review Paper) (Impact Factor: 1.512)
  14. Mayank Shrivastava, Harald Gossner and V. Ramgopal Rao, “A Novel Drain Extended FinFET Device for High Voltage High Speed Applications”, IEEE Electron Device Letters, Vol. 33, Issue: 10, Pages: 1432-1434, October, 2012. (DOI:10.1109/LED.2012.2206791 ) (Impact Factor: 3.433)
  15. Mayank Shrivastava, Harald Gossner and Christian Russ, “A Novel Drain Extended NMOS Device with Spreading Filament under ESD Stress”, IEEE Electron Device Letters, Vol. 33, Issue: 9, Pages: 1294-1296,  September, 2012. (DOI:10.1109/LED.2012.2205553 ) (Impact Factor: 3.433)
  16. Mayank Shrivastava, Manish Agrawal, Sunny Mahajan, Harald Gossner, Thomas Schulz, Dinesh Kumar Sharma, and V. Ramgopal Rao, “Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures”, IEEE Transactions on Electron Devices, Vol. 59, Issue: 5, Pages: 1353-1363, May, 2012. (DOI:10.1109/TED.2012.2188296 ) (Impact Factor: 2.62)
  17. Mayank Shrivastava, Ruchit Mehta, Shashank Gupta, M. Shojaei Baghini, D. K. Sharma, Harald Gossner, T. Schulz, K. Arnim, W. Molzer, V. Ramgopal Rao, “Towards System On Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 6, Pages: 1597-1607, June, 2011. (DOI:10.1109/TED.2011.2123100) (Impact Factor: 2.62) (This paper is recognized as feature article in Synopsys newsletter, May 2011)
  18. Ram Asra, Mayank Shrivastava, K. V. R. M. Murali, R. K. Pandey, Harald Gossner and V. Ramgopal Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 7, Pages: 1855-1863, July, 2011. (DOI:10.1109/TED.2011.2140322) (Impact Factor: 2.62)
  19. Rajesh A. Thakker, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, and Mahesh B. Patil, ” A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs”, Microelectronics Journals, Vol. 42, Issue: 5, Pages: 758–765, May, 2011. (https://doi.org/10.1016/j.mejo.2011.01.010) (Impact Factor: 1.332, Five-Year Impact Factor: 1.290)
  20. Mayank Shrivastava, Ruchil Jain, M. Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Solution towards the OFF state degradation in Drain extended MOS device”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 12,Pages:  3536-3539, December, 2010. (DOI:10.1109/TED.2010.2082549) (Impact Factor: 2.62)
  21. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 2, Pages: 309 – 317, February, 2011. (DOI:10.1109/TED.2010.2093010) (Impact Factor: 2.62)
  22. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, ” An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II(Two-Dimensional Study-Biasing & Comparison With NMOS)”, IEEE Transactions on Electron Devices, Vol. 58, Issue: 2, Pages: 318 – 326, February, 2011. (DOI:10.1109/TED.2010.2093011) (Impact Factor: 2.62)
  23. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part I: On the Behavior of STI-Type DeNMOS Device under ESD Conditions”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 9, Pages: 2235 – 2242, September 2010. (DOI:10.1109/TED.2010.2055276) (Impact Factor: 2.62)
  24. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 9, Pages: 2243 – 2250, September 2010. (DOI:10.1109/TED.2010.2055278) (Impact Factor: 2.62)
  25. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “A novel bottom spacer FinFET structure for improved power-delay & short channel performance”, IEEE Transactions on Electron Devices, Vol. 57, Issue: 6, Pages: 1287-1994, June 2010. (DOI:10.1109/TED.2010.2045686) (Impact Factor: 2.62)
  26. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART I-“Mixed Signal Performance of Various High Voltage Drain Extended MOS devices” IEEE Transactions on Electron Devices, Vol. 57, Issue: 2, Pages: 448-457, Feb 2010. (DOI:10.1109/TED.2009.2036796) (Impact Factor: 2.62)
  27. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “PART II-“A Novel scheme to optimize the mixed signal performance and hot carrier reliability of Drain Extended MOS devices” IEEE Transactions on Electron Devices, Vol. 57, Issue: 2, Pages: 458-465, Feb 2010. (DOI:10.1109/TED.2009.2036799) (Impact Factor: 2.62)
  28. Mayank Shrivastava, Maryam Shojaei Baghini, A. Sachid, Dinesh Kumar Sharma, V. Ramgopal Rao, “A Novel and Robust Approach for Common Mode Feedback using IDDG FinFET”, IEEE Transactions on Electron Devices, Vol, 55, Issue: 11,Pages: 3274-3282, Nov 2008. (DOI:10.1109/TED.2008.2004475). (Impact Factor: 2.62)

 

Peer Reviewed International IEEE Conferences with Proceedings (Available On IEEE Xplore)

  1. Jeevesh Kumar, Adil Meersha, Ansh and Mayank Shrivastava, “A First Principle Insight into Defect Assisted Contact Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, to appear in 24th IEEE SISPAD, Italy, 2019
  2. Nagothu Karmel Kranthi, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Performance and Reliability Co-Design of LDMOS-SCR for Self-Protected High Voltage Applications on-Chip”, 31st IEEE Intl. Symposium on Power Semiconductor Devices & ICs, May 19-23, 2019. DOI: 10.1109/ISPSD.2019.8757641
  1. Nagothu Karmel Kranthi, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Current Filament Dynamics Under ESD Stress in High Voltage (Bidirectional) SCRs and Its Implications on Power Law Behavior”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720484
  2. Abhishek Mishra, Adil Meersha, N. K. Kranthi, Kruti Trivedi, Harsha B. Variar, Veena Bellamkonda, Srinivasan Raghavan and Mayank Shrivastava, “First Demonstration and Physical Insights into Time-dependent Breakdown of Graphene Channel and Interconnects”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720452
  3. Sayak Dutta Gupta, Vipin Joshi, Srinivasan Raghavan and Mayank Shrivastava, “UV-Assisted Probing of Deep-Level Interface Traps in GaN MISHEMTS and Its Role In Threshold Voltage & Gate Leakage Instabilities”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720595
  4. Nagothu Karmel Kranthi, B. Sampath Kumar, Akram Salman, Gianluca Boselli and Mayank Shrivastava, “Physical Insights into the Low Current ESD Failure of LDMOS-SCR and Its Implication on Power Scalability”, 57th IEEE International Reliability Physics Symposium (IRPS), Monterey, California, USA, March 31 – April 4, 2019. DOI: 10.1109/IRPS.2019.8720580
  5. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, Swati Shikha, Sandeep Singh, Srinivasan Raghavan and Mayank Shrivastava, “Time Dependent Early Breakdown of AlGaN/GaN Epi Stacks and Shift in SOA Boundary of HEMTs Under Fast Cyclic Transient Stress”, 64th IEEE International Electron Device Meeting (IEDM)– 2018, CA, USA, DOI: 10.1109/IEDM.2018.8614690
  6. B. Shankar, A. Soni, S. Dutta Gupta, R. Sengupta, H. Khand, N. Mohan, S. Raghavan, N. Bhat, and Mayank Shrivastava, “Design and Reliability of GaN Power HEMT Technology”, AiMES 2018 Meeting (September 30 – October 4, 2018) (Invited) http://ma.ecsdl.org/content/MA2018-02/16/713.short
  7. B Sampath Kumar, Milova Paul, Harald Gossner and Mayank Shrivastava, “Physical Insights into the ESD Behavior of Drain extended FinFETs”, to appear in 40th EOSESD Symposium, Sep. 23rd to 28th 2018, Reno, NV, USA DOI: 10.23919/EOS/ESD.2018.8509695
  8. Bhawani Shankar, Rahul Singh, Rudrarup Sengupta, Heena Khand, Ankit Soni, Sayak D. Gupta, Srinivasan Raghavan and Mayank Shrivastava, “Trap Assisted Stress Induced ESD Reliability of GaN Schottky Diodes”, to appear in 40th EOSESD Symposium, Sep. 23rd to 28th 2018, Reno, NV, USA DOI: 10.23919/EOS/ESD.2018.8509745
  9. Bhawani Shankar, A. Soni, S. D. Gupta and Mayank Shrivastava, “Safe Operating Area (SOA) Reliability of Polarization Super Junction (PSJ) GaN FETs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353595
  10. Milova Paul, B. Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Contact and Junction Engineering in Bulk FinFET Technology for Improved ESD/Latch-up Performance with Design Trade-offs and Its Implications on Hot Carrier Reliability”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353573
  11. Bhawani Shankar, Ankit Soni, Sayak Dutta Gupta, R. Sengupta, H. Khand, N. Mohan, Srinivasan Raghavan and Mayank Shrivastava, “On the Trap Assisted Stress Induced Safe Operating Area Limits of AlGaN/GaN HEMTs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353596
  12. N. K. Kranthi, Abhishek Mishra, Adil Meersha, Harsha B. Variar and Mayank Shrivastava, “Defect-Assisted Safe Operating Area Limits and High Current Failure in Graphene FETs”, 56th IEEE International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353571
  13. Rajat Sinha, Prasenjit Bhattacharya, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of a-Si:H based Thin-Film Transistors: Physical Insights, Design and Technological Implications”, 56th IEEE  International Reliability Physics Symposium (IRPS), San-Francisco, USA, March 11th – 15th, 2018 DOI: 10.1109/IRPS.2018.8353572
  14. Sampath Kumar B, Milova Paul, Harald Gossner and Mayank Shrivastava, “Performance and Reliability Insights of Drain Extended FinFET Devices for High Voltage SoC Applications”, 30th Int’l Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, USA, May 13-17, 2018. DOI: 10.1109/ISPSD.2018.8393605
  15. Karmel Kranthi Nagothu, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “On the ESD Reliability issues in Carbon electronics: Graphene and Carbon Nano Tubes”, 31st International Conference on VLSI Design (VLSID), Jan 2018. DOI: 10.1109/VLSID.2018.117
  16. Vipin Joshi, Bhawani Shankar, Shree Prakash Tiwari and Mayank Shrivastava, “Dependence of Avalanche Breakdown on Surface & Buffer Traps in AlGaN/GaN HEMTs”, 22nd IEEE SISPAD, Japan, September 7-9, 2017 DOI: 10.23919/SISPAD.2017.8085276
  17. B. Sampath Kumar, Milova Paul and Mayank Shrivastava, “On the Design Challenges of Drain Extended FinFETs for Advance SoC Integration”, 22nd IEEE SISPAD, Japan, September 7-9, 2017 DOI: 10.23919/SISPAD.2017.8085296
  18. Adil Meersha, Harsha B Variar, Krishna Bharadwaj, Abhishek Mishra, Srinivasan Raghavan, Navakanta Bhat and Mayank Shrivastava, “Record Low Metal – (CVD) Graphene Contact Resistance Using Atomic Orbital Overlap Engineering”, Proceedings of IEEE International Electron Device Meeting, Dec. 5th – Dec. 7th, San Francisco, CA, USA, 2016 DOI: 10.1109/IEDM.2016.7838352
  19. N. K. Kranthi, Abhishek Mishra, Adil Meersha and Mayank Shrivastava, “ESD Behavior of Large Area CVD Graphene RF Transistors: Physical Insights and Technology Implications”, Proceedings of 55th IEEE International Reliability Physics Symposium, USA, April 4th – April 6th, 2017  DOI: 10.1109/IRPS.2017.7936298
  20. Bhawani Shankar, Ankit Soni, Manikant Singh, Rohith Soman, Hareesh Chandrasekar , Nagaboopathy Mohan, Neha Mohta, Nayana Ramesh, Shreesha Prabhu, Abhay Kulkarni, Digbijoy Nath, R. Muralidharan, K. N. Bhat, Srinivasan Raghavan, Navakant Bhat and Mayank Shrivastava, “Trap Assisted Avalanche Instability and Safe Operating Area Concerns in AlGaN/GaN HEMTs”, Proceedings of 55th IEEE International Reliability Physics Symposium, USA, April 4th – April 6th, 2017 DOI: 10.1109/IRPS.2017.7936414
  21. Milova Paul, B. Sampath Kumar, Christian Russ, Harald Gossner and Mayank Shrivastava, “FinFET SCR: Design Challenges and Novel Fin SCR Approaches for On-Chip ESD Protection”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073437
  22. Bhawani Shankar, Rudrarup Sengupta, Sayak Dutta Gupta, Ankit Soni, Nagaboopathy Mohan, Navakant Bhat, Srinivasan Raghavan and Mayank Shrivastava, “On the ESD Behavior of AlGaN/GaN Schottky Diodes and Trap Assisted Failure Mechanism”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073423
  23. Rajat Sinha, N.K. Kranthi, Sanjiv Sambandan and Mayank Shrivastava, “On the ESD Behavior of Pentacene Channel Organic Thin Film Transistor”, Proceedings of 39th EOSESD Symposium, September 2017, Sep. 12th – Sep. 15th, USA DOI: 10.23919/EOSESD.2017.8073426
  24. Abhishek Mishra and Mayank Shrivastava, “Unique Current Conduction Mechanism through Multi Wall CNT Interconnects under ESD Conditions”, Proceedings of 38th EOSESD Symposium, Anaheim, CA, USA, 11th – 14th September, 2016 DOI: 10.1109/EOSESD.2016.7592528
  25. Abhishek Mishra and Mayank Shrivastava, “New Insights on the ESD Behavior and Failure Mechanism of Multi Wall CNTs”, Proceedings of 54th IEEE International Reliability Physics Symposium, Pasadena, CA, USA, 17th – 19th April, 2016 DOI: 10.1109/IRPS.2016.7574609
  26. Bhawani Shankar and Mayank Shrivastava, “Unique ESD Behavior and Failure Modes of AlGaN/GaN HEMTs”, Proceedings of 54th IEEE International Reliability Physics Symposium, Pasadena, CA, USA, 17th – 19th April, 2016 DOI: 10.1109/IRPS.2016.7574608
  27. Milova Paul, Christian Russ, B Sampath Kumar, Harald Gossner and Mayank Shrivastava, “Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 (Received outstanding research paper award) DOI: 10.1109/VLSID.2017.32
  28. Bhawani Shankar and Mayank Shrivastava, “ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 DOI: 10.1109/VLSID.2017.57
  29. Adil Meersha, Sathyajit B and Mayank Shrivastava, “A Systematic Study on the Hysteresis Behavior and Reliability of MoS2 FET”, Proceedings of IEEE VLSI Design Conference, Jan. 8th – 11th, 2017 DOI: 10.1109/VLSID.2017.67
  30. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, “Device-Circuit Co-design for High Performance Level Shifter by Limiting Quasi-saturation Effects in Advanced DeMOS Transistors”, IEEE INEC, 9th – 11th, May, 2016, China DOI: 10.1109/INEC.2016.7589264
  31. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology mounted in BGA Package”, Proceedings of IEEE VLSI Design Conference, Jan. 2016 DOI: 10.1109/VLSID.2016.30
  32. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “On the Breakdown Physics of Trench-Gate Drain Extended NMOS”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore. DOI: 10.1109/EDSSC.2015.7285240
  33. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, “Comparison of Breakdown Characteristics of DeNMOS Devices with Various Drain Structures”, Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, June 2015, Singapore. DOI: 10.1109/EDSSC.2015.7285222
  34. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, “Drain Extended MOS Device Design for Integrated RF PA in 28nm CMOS with Excellent FoM and ESD Robustness”, Proceeding of IEEE International Electron Device Meeting (IEDM) Dec. 2014, San Francisco, CA, USA. DOI: 10.1109/IEDM.2014.7046974
  35. Mayank Shrivastava and Harald Gossner, “ESD Behavior of Metallic Carbon Nanotubes”, Proceedings of 36th EOSESD Symposium, 7th – 12th Sep. 2014, Tucson, Arizona, USA. INSPEC Accession Number: 14789864
  36. Mayank Shrivastava, Christian Russ, Harald Gossner, S. Bychikhin, D. Pogany and E. Gornik, “ESD Robust DeMOS Devices in Advanced CMOS Technologies”, Proceedings of EOSESD symposium, 11th – 15th Sep. 2011, Anaheim, California, USA. NSPEC Accession Number: 12316388
  37. Junjun Li, Rahul Mishra, Mayank Shrivastava, Yang Yang, Robert Gauthier, Christian Russ, “Technology Scaling Effects of Silicide-blocked PMOSFET Devices under ESD like conditions in Advanced Nanometer Node Bulk CMOS Technologies”, Proceedings of EOSESD Symposium, 11-15 Sep. 2011, Anaheim, California, USA INSPEC Accession Number: 12316385.
  38. Mayank Shrivastava, Christian Russ, Harald Gossner, “On the Impact of ESD Implant and Filament Spreading in Drain extended NMOS devices”, International ESD Workshop, May 2011, Lake Tahoe, CA, USA.
  39. Mayank Shrivastava, Manish Agrawal, Jasmin Aghassi, Harald Gossner, Wolfgang Molzer, Thomas Schulz, V. Ramgopal Rao, “On the thermal failure in nanoscale devices: Insight towards Heat Transport and Design Guidelines for Robust Thermal Management & EOS/ESD Reliability”, Proceedings of IEEE International Reliability Physics Symposium, 10-14 April, 2011, Monterey, CA, USA. DOI: 10.1109/IRPS.2011.5784498
  40. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “On the Transient Behavior of Various Drain Extended MOS Devices under the ESD stress conditions”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited) DOI: 10.1109/SOCDC.2010.5682922
  41. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, “3D TCAD based approach for the Evaluation of Nanoscale Devices during ESD Failure”, Proceedings of 7th International SoC Design Conference (ISOCC 2010), November 22-23, 2010, Songdo Convensia, Incheon, Korea (Invited) DOI: 10.1109/SOCDC.2010.5682919
  42. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA. DOI: 10.1109/IRPS.2010.5488723
  43. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “On the differences between 3D filamentation and failure of n & p type drain extended MOS devices under ESD condition”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), May 2nd – 6th, 2010, Anaheim, California, USA. DOI: 10.1109/IRPS.2010.5488785
  44. Mayank Shrivastava, Bhaskar Verma, M. Shojaei Baghini, Christian Russ, Dinesh K. Sharma, Harald Gossner, V. Ramgopal Rao, “Benchmarking the Device Performance at sub 22 nm node Technologies using an SoC Framework”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA. DOI: 10.1109/IEDM.2009.5424311
  45. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, “Filament Study of STI type Drain extended NMOS device using Transient Interferometric Mapping”, Proceedings of IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009, Baltimore, USA. DOI: 10.1109/IEDM.2009.5424337
  46. Mayank Shrivastava, Jens Schneider, Ruchil Jain, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “IGBT plugged in SCR device for ESD protection in advanced CMOS technology”, Proceedings of EOS/ESD symposium, August 30th – September 4th, 2009, Anaheim, CA, USA. INSPEC Accession Number: 10980103
  47. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “Highly resistive body STI: n-DEMOS: An optimized DEMOS device to achieve moving current filaments for robust ESD protection”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada. DOI: 10.1109/IRPS.2009.5173344
  48. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, “A New Physical Insight and 3D Device Modeling of STI Type DENMOS Device Failure under ESD Conditions”, Proceedings of IEEE International Reliability Physics Symposium (IRPS), April 26th – 30th, 2009, Montreal, Quebec, Canada. DOI: 10.1109/IRPS.2009.5173327

Other Peer Reviewed International Conferences

  1. A. B. Sachid, Mayank Shrivastava, R. A. Thakkar, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Asia Academic Forum 2008, Oct. 20th – Oct. 22nd 2008, Taipei, Taiwan. (Received the best research paper award).
  2. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, “Reliability aware I/O design for sub 45nm node CMOS technology”, IWPSD-2009, 15th -19th Dec, 2009 (Invited).
  3. Gaurav Sheoran, Jeevesh Kumar, Ansh, Srinivasan Raghavan and Mayank Shrivastava, “Universal approach to achieve enhanced ambipolar behaviour in all TMDs and CVD monolayer MoS2 based Field Effect Transistors (FETs)”, Graphene 2019, Rome, Italy, June 2019.
  4. Ansh, Jeevesh Kumar, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering: towards CMOS circuit integration of WSe2 FETs”, Graphene 2019, Rome, Italy, June 2019.
  5. Harsha Variar, Jeevesh Kumar, Ansh, Srinivasan Raghavan and Mayank Shrivastava, “Overall performance improvement of Transition Metal Dichalcogenides (TMDs) based Field-Effect Transistors (FETs) via Chalcogen assisted channel and contact engineering”, Graphene 2019, Rome, Italy, June 2019.
  6. Jeevesh Kumar, Ansh, Adil Meersha and Mayank Shrivastava, “A deep Insight into Defect Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, Graphene 2019, Rome, Italy, June 2019.
  7. Hemanjaneyulu Kuruva, Jeevesh Kumar and Mayank Shrivastava, “Improving the efficiency of MoS2 based FETs through Potassium Iodide doping”, Graphene 2019, Rome, Italy, June 2019.
  8. Ansh, Jeevesh Kumar, Gaurav Sheoran, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering: a universal approach to realize enhanced hole injection across CVD TMD monolayer – metal interfaces”, to appear in Graphene Week 2019, Finland, September 2019.
  9. Ansh, Jeevesh Kumar, Ravi K Mishra, Srinivasan Raghavan and Mayank Shrivastava, “Chalcogen assisted contact engineering led unique MIGS and DIGS at WSe2-metal interface enabling CMOS circuit integration of WSe2 transistors”, to appear in Graphene Week 2019, Finland, September 2019.
  10. Jeevesh Kumar, Ansh, Adil Meersha and Mayank Shrivastava, “A First Principle Insight into Defect Engineering at the Metal-Graphene and Metal-Phosphorene Interfaces”, to appear in Graphene Week 2019, Finland, September 2019.
  11. Jeevesh Kumar, Ansh and Mayank Shrivastava, “A First Principle Insight into Defect Assisted Band Gap Creation in Graphene”, to appear in Graphene Week 2019, Finland, September 2019.
  12. Abhishek Mishra, Adil Meersha, V Bellamkonda, G Sheoran, A Rao, Srinivasan Raghavan, Mayank Shrivastava, Investigation of Time-evolution of Electro-thermal Transport through Graphene-based Transistors and its Impact on the Device Reliability, to appear in Graphene Week 2019, Finland, September 2019.